Electrical computers and digital processing systems: processing – Architecture based instruction processing – Data flow based system
Reexamination Certificate
2000-10-26
2003-01-07
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Data flow based system
C712S033000, C711S202000, C711S206000, C710S120000
Reexamination Certificate
active
06505291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of processors. More specifically, the present invention relates to the subject matter of constituting the datapath and its control logic of a processor.
2. Background Information
Every processor has a datapath and a corresponding control logic. The term datapath as used herein is a collective reference to the processor elements employed in performing arithmetic logic operations, whereas the term control logic as used herein is a collective reference to the processor elements employed in controlling the datapath to effectuate the desired arithmetic logic operations. The term processor as used herein is intended to include microcontrollers (MCU), digital signal processors (DSP), general purpose microprocessors (&mgr;P), and the like. In the case of prior art processors, datapaths typically include arithmetic logic unit(s) (ALU), operand register or registers, control registers, and so forth. These prior art datapaths are typically controlled by control logic implemented in either hardwired logic or through microprogramming (also referred to as microcode or firmware).
The operand register(s) of a datapath varies (vary) from an accumulator approach, a stack approach or a register file approach. In the case of the stack based approach, one of the source as well as the destination operands of an instruction are implicitly defined to be located at the top of the stack, whereas, in the case of the accumulator based approach, one of the source as well as the destination operand of an instruction are implicitly defined to be located in the accumulator. Typically, the other source operand is located in a register. In the case of the register set based approach, the source and the destination operands of an instruction are either located in registers or in memory locations. While registers are specified by their identifiers, memory locations, whether cached or not, are specified by either physical or virtual addresses, depending on the manner in which memory is managed.
While the stack based approach enjoys the advantage of providing a simple model for expression evaluation, and short instruction, the approach suffers from at least the disadvantages of forcing all the operands onto the stack, and yet not being able to randomly access the pushed down operands in the stack, resulting in inefficient coding. As to the accumulator approach, while it minimizes the internal states of a processor, and provides for short instructions, it also suffers from at least the disadvantage of very high memory traffic, since the accumulator is the only temporary storage. The register based approach has the advantage of being the most general model for code generation, however, because of the access and related circuitry required to support a register, most prior art register based processors tend to provide only a limited number of registers, resulting in a relatively small working set. The disadvantage becomes especially limiting for heavily pipelined super-scalar processors.
With respect to the control logic, in the case of a hardwired implementation, typically one or more random control logic block are employed to generate the proper control signals to be output to control the datapath. The proper control signal to be output at a particular clock cycle is selected based on the current state of the processor, feedback from the datapath and the opcode of the next instruction to be executed. In the case of microprogrammed control logic, typically microinstructions are employed to specify the control signals for the datapath. The microinstructions are stored e.g. in a read-only-memory (ROM), and selected for output in each clock cycle, based on the current microinstruction program counter (PC). At each clock cycle, the microinstruction PC is modified based on a newly computed next microinstruction PC, the current microinstruction output (specifying in part the next microinstruction to be output), feedback from the datapath, and/or the opcode of the next instruction to be executed (also referred to as the next macroinstruction).
As a result, a processor designer has to operate and optimize the processor being designed at a pretty low level, which translates into complexity and low productivity. Furthermore, the processor designer has to employ different methodologies for the datapath and its control logic, which further compounds the complexity and low productivity problem. Thus, a more effective approach to designing and implementing a processor's datapath and its control logic without some of the prior art disadvantages is desired.
SUMMARY OF THE INVENTION
A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU.
In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.
REFERENCES:
patent: 3766532 (1973-10-01), Liebel, Jr.
patent: 4525780 (1985-06-01), Bratt et al.
patent: 4901235 (1990-02-01), Vora et al.
patent: 4905141 (1990-02-01), Brenza
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 5179734 (1993-01-01), Candy et al.
patent: 5185878 (1993-02-01), Baror et al.
patent: 5218707 (1993-06-01), Little et al.
patent: 5228135 (1993-07-01), Ikumi
patent: 5274770 (1993-12-01), Khim Yeoh et al.
patent: 5287490 (1994-02-01), Sites
patent: 5313413 (1994-05-01), Bhatia et al.
patent: 5369772 (1994-11-01), Tubbs
patent: 5375209 (1994-12-01), Maher et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5408622 (1995-04-01), Fitch
patent: 5430862 (1995-07-01), Smith et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5450555 (1995-09-01), Brown, III et al.
patent: 5450607 (1995-09-01), Kowalczyk et al.
patent: 5463745 (1995-10-01), Vidwans et al.
patent: 5509130 (1996-04-01), Trauben et al.
patent: 5511182 (1996-04-01), Le et al.
patent: 5517665 (1996-05-01), Sprague et al.
patent: 5530889 (1996-06-01), Kametani
patent: 5544092 (1996-08-01), Gunther et al.
patent: 5557760 (1996-09-01), Nishii et al.
patent: 5568401 (1996-10-01), Narayanaswami
patent: 5574873 (1996-11-01), Davidian
patent: 5574927 (1996-11-01), Scantlin
patent: 5619667 (1997-04-01), Henry et al.
patent: 5701432 (1997-12-01), Wong et al.
patent: 5724550 (1998-03-01), Stevens
patent: 5742802 (1998-04-01), Harter et al.
patent: 5752073 (1998-05-01), Gray, III et al.
patent: 5758183 (1998-05-01), Scales
patent: 5761484 (1998-06-01), Agarwal et al.
patent: 5768624 (1998-06-01), Ghosh
patent: 5774710 (1998-06-01), Chung
patent: 5787478 (1998-07-01), Hicks et al.
patent: 5825074 (1998-10-01), Blomgren
patent: 5893147 (1999-04-01), Deng
patent: 5909695 (1999-06-01), Wong et al.
patent: 5923894 (1999-07-01), Sollars
patent: 5940626 (1999-08-01), Sollars
patent: 5946710 (1999-08-01), Bauman et al.
patent: 6016539 (2000-01-01), Sollars
patent: 6178482 (2001-01-01), Sollars
patent: 6216218 (2001-04-01), Sollars
Computer Architecture and Quantitative Approach; Authors: John L Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 3, entitled “Instruction Set Design: Alternatives and Principles”, pp. 89-137.
Computer Architecture and Quantitative Approach; Authors: John L. Hennessey, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 5, entitled “Basic Processor Implementation Techniques”, pp. 199-248.
Paten Cooperation Treaty's International Search Report for International Application No. PCT/US99/15274, dated Oct. 6, 1999.
Blakely Sokoloff Taylor & Zafman LLP.
Brecis Communications
Pan Daniel H.
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