Processor for two-dimensional array antenna

Communications: directive radio wave systems and devices (e.g. – Directive – Including a steerable array

Reexamination Certificate

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Details

C342S368000, C342S375000

Reexamination Certificate

active

06255990

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to radio signal antennas, and more particularly relates to signal processors for two-dimensional array antennas.
BACKGROUND OF THE INVENTION
It is well known in the prior art that antennas for radiating and receiving radio signals may be formed from several individual antenna elements. By arranging the antenna elements with specific geometry, and combining signals associated with the individual elements with a specific phase and amplitude relationship, the individual elements cooperate to form a unitary antenna structure.
Each of the individual antenna elements in such an antenna (in a transmit application) radiates a signal which is common in frequency, but altered in amplitude and phase from the other elements. As a result, the individual signals combine in space at varying phase and amplitude levels to create an antenna pattern. The signal combination essentially follows a three dimensional vector addition function. The combination of signals which are in phase results in signal lobes. The cancellation of signals which are completely out of phase (i.e., 180°) results in signal nulls. For all phase angles in between these extremes, partial cancellation occurs which shapes the signal lobes. The resultant signal is referred to as the antenna pattern. The antenna pattern is characterized by the number of lobes, thc magnitude of the lobes (gain), the direction of the lobes and the relative magnitude of the lobes in differing directions (directivity).
In multi-element array antennas, the gain, directivity and lobe direction may be varied by controlling the phase of the signals driving the individual elements. This type of antenna is conventionally referred to as a phased array. An in depth treatment of conventional phased arrays is presented in The Radar Handbook, Second Edition, edited by Merrill Skolnik, published in 1990 by McGraw-Hill, which is incorporated herein by reference.
Phased arrays may be formed as linear arrays (FIG.
1
), planar arrays (FIG.
2
), or conforming arrays (FIG.
3
). The linear array shown in
FIG. 1
is capable of producing an antenna pattern which can be rotated along (scanned) a two dimensional plane by varying the phase of the signals driving each of the antenna elements
2
. The planar and conforming arrays are capable of scanning in three dimensional space by appropriately driving the individual antenna elements
2
.
Regardless of the chosen array geometry, the signal along each path between a signal source and the antenna elements have a controlled phase relationship in order to form a desired antenna pattern. This is achieved by controlling signal power division ratios and the phase shift in the electrical transmission path between the signal source and each antenna element. A structure which performs this function is generally referred to as an antenna feed or processor.
FIG. 4
illustrates a conventional “corporate feed” antenna feed topology. In a corporate feed, a signal source
4
simultaneously drives, in parallel, each of the antenna elements
2
. In a corporate feed, the length of each transmission line segment
6
is the same for each antenna element
2
. The phase of the signal driving each element is controlled by an analog phase shift network
8
. For a variable antenna pattern, each antenna element
2
will have an individually controllable phase shift network
8
.
An alternative antenna feed network, a series feed, is illustrated in FIG.
5
. In the conventional series feed network, a series of antenna elements
2
are connected in a single transmission line
6
with a built in phase progression between the antenna elements
2
. The phase progression is determined in part by the length of the transmission line
6
(physical path length) between successive antenna elements
2
. The phase of the signal at each element
2
is related to the electrical path length between antenna elements
2
. The electrical path length, expressed in wavelengths, changes with frequency for a fixed physical path length. Therefore, the phase progression between antenna elements
2
in a series feed varies with frequency. For variable antenna patterns, variable analog phase shift networks
8
may be inserted between the antenna elements
2
.
A third conventional antenna feed network, a space feed network, is illustrated in FIG.
6
. In the space feed network, a source antenna
10
is electrically connected to a signal source
4
. The source antenna
10
radiates a signal received from the signal source
4
. The radiated signal is received by a series of pickup elements
12
. The received signals are then coupled through phase and amplitude shift networks
9
to the antenna elements
2
for transmission.
The antenna feed topologies illustrated in
FIGS. 4
,
5
and
6
each require the use of phase shift networks or time delay devices in line with each antenna element to achieve dynamic antenna pattern control or scanning. Thus, in a large two-dimensional array antenna of M*N elements, M*N phase shift networks are required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a signal processor for two-dimensional array antennas.
It is a further object of the present invention to provide a signal processor for two-dimensional array antennas that form transmit or receive beams using a relatively small number of phase shifters for a given number of antenna elements.
It is another object of the present invention to provide a signal processor for two-dimensional array antennas that support multiple transmit or receive beams using a relatively small number of phase shifters for a given number of antenna elements.
In accordance with the present invention, a processor is formed for an array antenna having antenna elements arranged in a number of row positions equal to M and a number of column positions equal to N, for receiving an incident beam signal. The processor includes a plurality of frequency translation circuits which are operatively coupled to the antenna elements and shift an incident beam signal to one of a plurality of column intermediate frequencies. The processor also includes M row processing circuits, responsive to signals from the frequency translation circuits associated with elements in corresponding rows of the array. Each row processing circuit imparts a delay in accordance with the corresponding row position. A summing circuit is coupled to the row processing circuits and provides a row signal. The processor includes a column processing circuit which is responsive to the row signal, partitions the row signal into N column signals in accordance with the column intermediate frequencies, and imparts a delay on the column signals in accordance with the column position. The processor shifts the column intermediate frequency signals to a common frequency and those signals are applied to a second summing circuit which forms a received signal output signal representing the incident beam signal.
Preferably, each of the row processing circuits includes a row summing circuit for receiving signals from the antenna elements in a corresponding row position and a row delay circuit for receiving the signal from the corresponding row summing circuit and imparting a delay in accordance with the corresponding row position.
The column processing circuit can include a filter bank, which has an input for receiving the row signal and N output ports for selectively partitioning the row signal in accordance with the N column intermediate frequencies. The column processing circuit can also include N column delay circuits which are operatively coupled to a corresponding filter bank output port and impart a delay in accordance with a corresponding column position. N column frequency translation circuits can also be included, with each column frequency translation circuit being responsive to one of the column intermediate frequencies and translating same to a common receive frequency.
The above processor can be adapted to receive multiple beam signals. In this embodiment, the N col

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