Processor for selectively performing multiplication/division

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364764, G06F 752

Patent

active

057779074

ABSTRACT:
A processor 10 for selectively performing multiplication or division of two inputs comprises a pre-processing unit 20 for modifying the signs of the inputs; an aligning unit 30 for aligning bit positions of the sign-modified inputs; an arithmetic unit 40 for selectively performing multiplication or division of the sign-modified and bit-aligned inputs; a post-processing unit 50 for modifying the signs of outputs from the arithmetic unit; and a control unit 70 for controlling operations of the pre-processing unit, aligning unit, arithmetic unit, and post-processing unit.

REFERENCES:
patent: 3535498 (1970-10-01), Smith, Jr.
patent: 4441158 (1984-04-01), Kanuma
patent: 5270962 (1993-12-01), Fettweis
patent: 5444647 (1995-08-01), Komoda

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