Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2002-12-17
2008-11-18
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S210000, C712S221000
Reexamination Certificate
active
07454594
ABSTRACT:
A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in parallel by a SIMD arithmetic unit. A selector for adding an operation for interchanging multiple outputs of a SIMD arithmetic unit is added to a data path. A register file is divided in accordance with the output bit fields of the SIMD arithmetic unit. A means of specifying multiple registers as a SIMD instruction's output operand is added. Therefore, part of the output results of arithmetic operations performed in parallel by the SIMD arithmetic unit can be stored in a register providing the input for another arithmetic operation. Software pipelining is rendered achievable in this manner.
REFERENCES:
patent: 5822619 (1998-10-01), Sidwell
patent: 6122725 (2000-09-01), Roussel et al.
patent: 0 930 564 (1998-04-01), None
patent: 50-43853 (1973-08-01), None
patent: WO 98/45774 (1998-04-01), None
A. Marquez, Esq. Juan Carlos
Chan Eddie P
Fennema Robert E
Fisher Esq. Stanley P.
Reed Smith LLP
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