Television – Bandwidth reduction system – Data rate reduction
Patent
1995-10-06
1998-10-20
Lee, Richard
Television
Bandwidth reduction system
Data rate reduction
348250, H04N 730
Patent
active
058254200
ABSTRACT:
A processor is provided for transforming N.times.N discrete cosine transform (DCT) coefficients F.sub.uv inputted from a run-length-code 5 (RLC) decoder and arranged in an input order into an image data f.sub.jk in an integrated circuit through a 2-D inverse discrete cosine transform (IDCT) procedure wherein subscripts u and v of DCT coefficients F.sub.uv are input frequency indices respectively having least significant bits (LSB) u.sub.0 and v.sub.0 having an exclusive-OR (XOR) and subscripts j and k of image data f.sub.jk are spatial indices generated by the integrated circuit, which comprises a cosine pre-multiplier array for computing cosine-weighted DCT coefficients, a principal subkernel mapper utilizing the cosine-weighted DCT coefficients by first referring to the indices u and v for forming a principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv, an N.times.N accumulating matrix operating with the principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv for progressively accumulating the image data f.sub.jk, and an output buffer for loading the image data f.sub.jk from the N.times.N accumulating matrix and transferring the image data f.sub.jk. Such a processor will reduce the number of the multipliers involved and simplify the hardware complexity therefor, fasten the pixel rate thereof so that the present method is especially suitable for the future HDTV systems, be able to progressively transform the arbitrary input order of DCT coefficients thereof so that the present method is especially suitable for the HDTV recording player systems and has an excellent regularity thereof and applies a simple hardware architecture so that the cost for the hardware is relatively low and the method is suitable for the manufacturing of VLSI for the HDTV systems.
REFERENCES:
patent: Re34734 (1994-09-01), Cambonie
patent: 5063608 (1991-11-01), Siegel
patent: 5257213 (1993-10-01), Kim et al.
patent: 5299025 (1994-03-01), Shirasawa
patent: 5319724 (1994-06-01), Blonstein et al.
patent: 5345408 (1994-09-01), Hoogenboom
patent: 5452466 (1995-09-01), Fettweis
patent: 5515388 (1996-05-01), Yagaski
patent: 5576765 (1996-11-01), Cheney et al.
M. A. Hague, "Two-Dimension Fast Cosine Transform", IEEE Trans. on Acoustica Speech, and Signal Processing, vol. ASSP. 33, No. 6, Dec. 1985, pp. 1532-1538.
U. Totzek, F. Matthiesen, "Two-dimesional Discrete Cosine Transformation with Linear Systolic Arrays", Systolic Array Processors, pp. 388-397, Prentice Hall, 1989.
Bai Bor-Long
Yang Jar-Ferr
Lee Richard
National Science Council
LandOfFree
Processor for performing two-dimensional inverse discrete cosine does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor for performing two-dimensional inverse discrete cosine, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor for performing two-dimensional inverse discrete cosine will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-250168