Processor for multiple cache coherent protocols

Details Processor for multiple cache coherent protocols Processor for multiple cache coherent protocols

1991-10-11

1994-04-05

Dixon, Joseph L.

Boots, shoes, and leggings

3642328, 3642329, G06F 1314

Patent

active

053012984

ABSTRACT:
An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

REFERENCES:
patent: 4484267 (1984-11-01), Fletcher
patent: 4622631 (1986-11-01), Frank et al.
patent: 4847804 (1989-07-01), Shaffer et al.
patent: 4939641 (1990-07-01), Schwartz et al.
patent: 5025366 (1991-06-01), Baror
patent: 5113510 (1992-05-01), Hillis
patent: 5140681 (1992-08-01), Uchiyama et al.
patent: 5146603 (1992-09-01), Frost et al.
patent: 5148533 (1992-09-01), Joyce et al.

Affiliated with

Also associated with

Rating

Processor for multiple cache coherent protocols does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor for multiple cache coherent protocols, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor for multiple cache coherent protocols will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-519564