Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2006-08-22
2006-08-22
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S203000, C712S229000
Reexamination Certificate
active
07096344
ABSTRACT:
The present invention provides a processor capable of carrying out a plurality of operation instructions simultaneously in one cycle which improves utilization of an instruction when carrying out a single operation instruction, and a system equipped with such a processor. In this processor, an operation mode indicating whether or not a coprocessor should be run in parallel is retained in an operation mode register, and in the integer processor operation mode, a value “0” is set in the operation mode register in an operation mode controller of an integer processor, and an instruction register delivers an integer processor instruction to a decoder, so that an execution unit will execute the integer processor instruction, and outputs a no operation instruction to a data processor without embedding an instruction that defines an operation thereof, and puts the data processor in the halt condition. On the other hand, in the parallel processing operation mode, a value “1” is set in the operation mode register in the operation mode controller, and the instruction register delivers the integer processor instruction to the decoder, and outputs a data processor instruction to the data processor to carry out data processing. Because the integer processor operation mode requires the integer processor instruction alone in the instruction string, utilization of the instructions can be improved.
REFERENCES:
patent: 5241636 (1993-08-01), Kohn
patent: 5452434 (1995-09-01), MacDonald
patent: 5535410 (1996-07-01), Watanabe et al.
patent: 5666537 (1997-09-01), Debnath et al.
patent: 5673409 (1997-09-01), Hicok et al.
patent: 5826054 (1998-10-01), Jacobs et al.
patent: 5838934 (1998-11-01), Boutaud et al.
patent: 5923892 (1999-07-01), Levy
patent: 6189090 (2001-02-01), Tan et al.
patent: 0 864 960 (1998-09-01), None
patent: 2 317 977 (1998-04-01), None
patent: 10-003425 (1998-01-01), None
patent: WO 99/14669 (1999-03-01), None
H. Sato, et al., IEEE International Conference on Acoustics, Speech and Signal Processing, vol. 1 XP-000789216, pp. 591-594, “A Dual-Issue Risc Processor for Multimedia Signal Processing”, Apr. 21, 1997.
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