Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Patent
1997-01-23
1999-07-20
Maung, Zarni
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
712 23, G06F 930
Patent
active
059251239
ABSTRACT:
A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.
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O'Connor James Michael
Tremblay Marc
Gunnison Forrest
Maung Zarni
McKay Philip J.
Sun Microsystems Inc.
Winder Patrice L.
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