Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-05-01
2001-03-27
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
Reexamination Certificate
active
06209079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor for executing an operation of a plurality of instruction codes and, more particularly, to a technique for locating instruction codes in a processor.
2. Description of the Background Art
Conventionally, instructions are stored as instruction codes in a memory connected to a processor through a data bus. The formats of the instruction codes stored in the memory are of two types: (1) a “fixed length instruction format” in which a constantly fixed instruction code length is set independently of instruction types, and (2) an “instruction format having an variable length” (referred to hereinafter as an variable length instruction format) in which different instruction code lengths are set depending upon the instruction types.
The instruction code has an operation code part for specifying the functions of the instructions such as operation, transfer, branch, and the like, and an operand code field for specifying the data on which the instruction is to be executed (operand). The operand is specified such that an addressing mode specifying part in the instruction code specifies whether the operand is located in a register or in an external memory. If the operand is located in the memory, address information is added to the contents of the instruction code.
FIGS. 18 and 19
schematically illustrate the fixed length instruction format and the variable length instruction format, respectively. In
FIGS. 18 and 19
, an instruction format
100
is the fixed length instruction format when the operand is absent, an instruction format
101
is the fixed length instruction format when the operand is present, an instruction format
102
is the variable length instruction format when the operand is absent, and an instruction format
103
is the variable length instruction format when the operand is present.
(1) Instruction Code Having Fixed Length Instruction Format
The instruction code having the fixed length instruction format is advantageous in easy decoding. However, the fixed length instruction format is restricted such that the operation code, the addressing mode specifying part, and additional information such as address information must be contained within a determined fixed instruction length range. Thus, storage of more additional information requires a greater instruction length. Consequently, the fixed length instruction format having the greater instruction length increases redundant portions in an instruction bit pattern, resulting in increased code size. On the other hand, a decreased instruction length for code size reduction results in severer restrictions on instruction functions.
(2) Instruction Code Having Variable Length Instruction Format
The instruction code having the variable length instruction format is advantageous in that the instruction functions may be expanded depending upon the instructions because of the use of the instruction formats of two or more arbitrary instruction lengths. Additionally, the instructions having no operand may be of a short length to permit the code size to be smaller than that for the fixed length instruction format.
On the other hand, the extraction of data read from a memory as instruction codes and decoding the instruction codes are complicated, resulting in a complicated instruction decoding method. This increases the amount of hardware for extracting the instruction codes from the contents of the memory to feed the extracted instruction codes to an instruction decoder. With reference to
FIG. 20
, for example, the introduction of a 16-bit instruction format
105
and a 32-bit instruction format
104
as the variable length instruction formats involves the need to provide four paths for transferring the instruction code between an instruction fetch portion and an instruction decoder as illustrated in FIG.
21
. For this purpose, the instruction decoder must have a complicated shift function so that an effective instruction code is shifted and decoded, with the instruction code properly located.
As above described, (1) the fixed length instruction format and (2) the variable length instruction format have advantages and drawbacks. The achievement of a processor having the advantages of both the fixed length instruction format and the variable length instruction format has been desired.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a processor comprises: instruction code input means having instruction codes consisting of first instruction data signals indicative of an N-bit instruction (where N is an integer not less than 1) and second instruction data signals indicative of a 2N-bit instruction, the instruction codes of the first and second instruction data signals being located under such rules that two of the first instruction data signals are stored within 2N-bit word boundaries and that each of the second instruction data signals is stored within the 2N-bit word boundaries; and instruction fetch means for fetching the instruction code input means to hold the instruction codes located under the rules.
Preferably, according to a second aspect of the present invention, the processor of the first aspect of the present invention further comprises: instruction decoding means for receiving data signals indicative of the instruction codes transferred from the instruction fetch means to restrictively specify a branch destination address for the instruction codes only on the 2N-bit word boundaries, thereby to decode the instruction codes.
Preferably, according to a third aspect of the present invention, in the processor of the second aspect of the present invention, low-order two bits of the branch destination address are constantly “00”.
Preferably, according to a fourth aspect of the present invention, in the processor of the second aspect of the present invention, each of the first and second instruction data signals has instruction length identifier indicative of control information of an instruction execution sequence at a predetermined bit position thereof.
Preferably, according to a fifth aspect of the present invention, in the processor of the fourth aspect of the present invention, the instruction decoding means comprises: an instruction decode input latch for storing the instruction code data signals transferred from the instruction fetch means with a width of 2N bits; an instruction decoder for receiving and decoding at least one instruction code data signal indicative of an effective instruction code among the instruction code data signals stored in the instruction decode input latch; and a control logic for controlling the transfer of the effective instruction code from the instruction decode input latch to the instruction decoder on the basis of the instruction length identifier indicated by the instruction code data signals stored in the instruction decode input latch.
Preferably, according to a sixth aspect of the present invention, in the processor of the fifth aspect of the present invention, the control logic controls the instruction decode input latch in such a manner that: when the instruction length identifier indicate that the instruction code data signals stored in the instruction decode input latch are the second instruction data signals, the control logic directly transfers the second instruction data signals from the instruction decode input latch to the instruction decoder; and when the instruction length identifier indicate that the instruction code data signals stored in the instruction decode input latch are two of the first instruction data signals which are effective, the control logic transfers one of the two first instruction data signals which is located in a high-order bit position from the instruction decode input latch to the instruction decoder, and then shifts the remainder of the two first instruction data signals which is located in a low-order bit position to the high-order bit position in which the former first instruction data signal has been located to transfer the
Iwata Shunichi
Otani Sugako
Burns Doane , Swecker, Mathis LLP
Eng David Y.
Mitsubishi Denki & Kabushiki Kaisha
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