Processor for executing arithmetic operations on input data and

Details Processor for executing arithmetic operations on input data and Processor for executing arithmetic operations on input data and

1987-10-30

1990-08-21

Shaw, Dale M.

Boots, shoes, and leggings

364736, 364746, 364748, G06F 102, G06F 772

Patent

active

049512382

ABSTRACT:
A process for carrying out modulo reduction of floating-point data uses a predetermined constant. A subtraction operation of more significant bits of the predetermined constant from a mantissa part of the floating-point data is performed and the subtraction result is normalized. Less significant bits of the predetermined constant are shifted and this result is subtracted from the above normalized data and is then normalized. Thus, a remainder resulting from the modulo reduction is obtained.

REFERENCES:
patent: 3997771 (1976-12-01), Perlowski et al.
patent: 4164022 (1979-08-01), Rattingoutd et al.
patent: 4231102 (1980-10-01), Barr et al.
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4777613 (1988-10-01), Shahan et al.
IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE STD 754-1985, New York, 1985.
John P. Hayes, "Computer Architecture and Organization", McGraw-Hill Book Company, 1978, pp. 240-241.

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