Processor for eliminating external isochronous subsystems

Details Processor for eliminating external isochronous subsystems Processor for eliminating external isochronous subsystems

1995-10-06

1998-11-17

Shah, Alpesh M.

395591, G06F 1576

Patent

active

058389873

ABSTRACT:
A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.

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CHIPSystem Architecture, Product Briefs, Oct. 1991, "The Super State.TM. Architecture," pp. 15-25.

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