Television – Image signal processing circuitry specific to television – Motion vector generation
Patent
1996-03-27
1998-09-08
Britton, Howard
Television
Image signal processing circuitry specific to television
Motion vector generation
348416, G06T 720, H04N 736
Patent
active
058052399
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Processors of this type are utilized in many applications in the field of motion estimation such as, for example, in hybrid coding for video compression or in a motion-compensated interpolation. A flexible solution is thereby desirable in order to support different methods but different parameter combination as well. Examples of this include underscanning in the shift field, investigation of what are referred to as candidate vectors and calculations with sub-pixel precision.
All-purpose digital signal processors or flexible video processors are usually designed neither for the required calculating performance nor for the required I/O bandwidths.
The high calculating performance required therefor can be produced with two-dimensional cell fields. Since, however, external data can only be supplied over the cell field edge in this case, the high calculating performance that is available can usually only be incompletely exploited, considerable usage losses resulting therefrom as a rule.
Up to now, high usage factors of, for example, up to 100% of said two-dimensional cell fields were hitherto achieved only given dedicated implementations of block-matching algorithms based on a complete search.
The publication, IEEE Transactions on Circuits and Systems, Vol. 36, No. 10, October 1989, pages 1309 through 1316 explains a parameterizable VLSI architecture for a block-matching algorithm that is based on a complete search in greater detail.
Given an incomplete search, i.e. when all possible shift vectors with a respective search region are not investigated, only one sub-set of the calculated results is required. Although a block-matching algorithm based on an incomplete search can be realized by a flexible selection of the relevant results or of the processor elements to be considered in the cell field, this occurs at the expense of substantial losses in the effective usage of the processor circuit.
European Patent Application 0 395 293 A1 (corresponding to U.S. Pat. No. 5,206,723) discloses a motion estimating means with comparison processors wherein, among other things, a minimum shift vector is calculated.
SUMMARY OF THE INVENTION
The object underlying the invention is then comprised in specifying a processor for comparing picture element blocks (block matching processor) with a two-dimensional cell field that also offers an optimally high hardware usage given block matching algorithms that are based on an incomplete search.
In general terms the present invention is a processor for comparing picture element blocks (block matching processor), whereby a block memory for data of two current picture element blocks, a search domain memory for data of picture elements of a part of a comparison image limited by two horizontally neighboring search domains, a respective search domain being composed of rows and columns, a two-dimensional processor/register cell field and a control unit are provided. The search domain memory is organized with respect to its word width such that the processor/register cell field is respectively supplied in parallel with data of picture elements of a complete column of the respective search domain per system clock. An amount is formed from a respective difference and the amounts are summed up. The search domain memory contains data of two search domains. The two search domains horizontally overlap one another in order to shorten a reloading of the processor/register cell field given a change of search domain. A control sequence is stored in the control unit that, per system clock, supplies parallel data flow control signals, an address for addressing the block memory, and a further address for addressing the respective search domain memory. The control unit is programmed by external control data. A shift register clocked by the system clock is provided. A flexible control sequence dependent on the respective comparison method (block matching algorithm) is written thereinto by the control data. The control sequence generates the output signals of the control unit
REFERENCES:
patent: 5206723 (1993-04-01), Parke
IEEE Transactions on Circuits and Systems, vol. 36, No. 10, Oct. 1989, Luc De Vos et al,Parameterizable VLSI Architectures for the Full-Search Block-Matching Algorithm, pp. 1309-1316.
De Vos Luc
Schobinger Matthias
Britton Howard
Siemens Aktiengesellschaft
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