Processor for a TDMA burst modem

Multiplex communications – Wide area network – Packet switching

Patent

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Details

370104, 255 12, H04J 306

Patent

active

042321972

ABSTRACT:
The present invention provides a processor for interfacing a TDMA burst modem (40), which transmits and receives bursts of information at high data rates in assigned time slots, and slow speed terminal processing equipment. The present processor comprises circuitry (50) capable of detecting frame or superframe markers in a received sequence and regenerating such markers, after initiation, at the normal interval for such markers despite false alarms or missed marker signals. Other circuitry (53, 57 and 52, 62) causes a memory (48, 56) to directly output a burst of information during an assigned time slot to the modem (40) and directly store received information from modem (40) during a predetermined interval which is designed to start before and end after the expected arrival of an assigned burst. Slower processing equipment is then used to find and process the burst in the stored information.

REFERENCES:
patent: 3532985 (1970-10-01), Glomb
patent: 3562432 (1971-02-01), Gabbard
patent: 3641274 (1972-02-01), Sasaki
patent: 3643031 (1972-02-01), Sasaki
patent: 3730998 (1973-05-01), Schmidt
patent: 3787634 (1974-01-01), Haberle
patent: 3995111 (1976-11-01), Tsuji
patent: 4054753 (1977-10-01), Kaul
IEEE Transactions on Communications, vol. com-16, No. 4, Aug. 1968, "Design of a Satellite Time Division Multiple Access Burst Synchronizer", by Gabbard, pp. 589-596.
Electronic Letters, vol. 9, No. 4, Nov. 1973, "New Snychronization Scheme for Communication-Satellite TDMA Systems", by A. K. Jefferis, pp. 566-568.

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