Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
1998-12-15
2002-01-15
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S027000, C712S226000, C712S227000, C717S152000
Reexamination Certificate
active
06339752
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is related to our copending patent applications assigned to the assignee hereof:
“DIFFERENT WORD SIZE MULTIPROCESSOR EMULATION” by David A. Egolf, filed Sep. 8, 1998, with Ser. No. 09/149,261, and
“PROCESSOR EMULATION VIRTUAL MEMORY ADDRESS TRANSLATION” by David A. Egolf, filed of even date herewith, with Ser. No. 09/212,968.
FIELD OF THE INVENTION
The present invention generally relates to computer system emulation, and more specifically to instruction fetch optimization in emulation of a Target system utilizing a multiprocessor Host system.
BACKGROUND OF THE INVENTION
The cost of designing a computer processor continues to increase. Some computer architectures thus ultimately become uneconomical to implement directly, despite these architectures having significant installed bases.
One solution to this problem is to simulate (or emulate) one computer architecture on another computer architecture. Herein, the simulating (or emulating) computer architecture will be termed the “Host” computer system, while the simulated (or emulated) computer architecture will be termed the “Target” computer system. Emulators have been available almost since the advent of the first compilers.
One problem that arises in emulating one computer architecture on another involves address translation. In virtual memory computer systems, it is necessary to translate from operand and instruction virtual addresses to real memory addresses. In older computer systems, this translation was rudimentary. As computer technology progressed, this translation of virtual addresses to real addresses has continued to become ever more complicated.
Full virtual to real address translation typically consumes significant computer cycles, whether done in hardware, or in an emulator. When emulating a complex computer architecture, such as the GCOS® 8 architecture provided to customers by the assignee herein, full virtual to real address translation may take upwards of a hundred instructions to accomplish. The problem is compounded by the necessity to translate at least two virtual addresses per instruction executed for most instructions executed or emulated: one to fetch the instruction to execute, and a second one for the instruction operand.
Hardware implementations have addressed this complexity and sped up the virtual to real address translations with a number of hardware assists that have been developed over time. One such hardware assist is the use of look-aside buffers, where recent operand and instruction addresses, along with their virtual to real address translations, are maintained. Instead of immediately doing virtual to real address translations, a search is made first of the look-aside buffer. If the virtual page address has been recently translated, the corresponding real page address for the operand or instruction can be taken from the look-aside buffer. This eliminates the repeated need for expensive virtual to real address translation. This ability to test or compare a number of addresses in parallel in hardware is well understood in the prior art, and is one of the fundamental bases for N-way set associative cache memories.
Software emulations typically cannot take advantage of this look-aside buffer strategy since Host systems seldom supply general-purpose associative memory capabilities. Instead, they must resort to a costly search to implement the same strategy. A pragmatic result is that an implementation which performs the full address development is in many cases cheaper than implementing the look-aside buffer technique.
When virtual to real address translation is done in software in an emulator, it is typically not possible on a Single Instruction/Single Data (SISD) processor to test or compare the virtual page address being translated against more than one previous virtual page address at a time. Thus, the previous virtual page addresses in the look-aside buffer would have to be tested sequentially. The result of this constraint is that it is often as expensive, or maybe even more expensive, in terms of computer cycles to utilize a look-aside buffer for caching virtual to real address translations as compared to performing full address translation for each address utilized.
It would thus be advantageous to be able to efficiently translate virtual to read addresses in an emulator. An efficient method of performing this address translation would significantly reduce the cost of emulating one (Target) computer system utilizing a second (Host) computer system.
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Jacob et al, “Virtual Memory: Issues of Implementation”, IEEE Computer Magazine, pp. 33-44 Jun. 1998.*
Bull HN Information Systems Inc. GC0S8 Operating System Programmers Guide-DPS 9000G Assembly Instructions, Mar. 1998, Preface iii to xi; pp. 3-1 to 3-24; 4-8, 4-11, 4-24 to 4-28; 4-32 to 4-34; 4-36 to 4-40; 4-50, 5-63 to 5-90.
Hayden Bruce E.
Mann George A.
Broda Samuel
Bull HN Information Systems Inc.
Hayden B. E.
Solakian J. S.
Teska Kevin J.
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