Processor device having automatic bus sizing

Details Processor device having automatic bus sizing Processor device having automatic bus sizing

1996-04-03

1998-06-02

Sheikh, Ayaz R.

Boots, shoes, and leggings

395325, 395500, 364578, 364443, 364579, G06F 1300

Patent

active

057614563

ABSTRACT:
A processor device and method for booting a programmable apparatus having a signal bus having a selectable bus width. The processor device includes a microprocessor, a configurable bus interface for coupling the microprocessor to the signal bus, and a first memory. The first memory includes a bus sizing code for instructing the microprocessor for reading initial data from a pre-determined address of a second memory and configuring the bus interface to the bus width that has been selected. The first memory further includes a checksum code for a self-test of the memory, an emulator detect code for skipping the checksum code when control of the microprocessor is transferred to an emulator, a delay code for delaying a start of operation of the programmable apparatus when circuits in the programmable apparatus have a restrictive voltage requirement, and a monitor request code for transferring control to a monitor code when requested by an external user or when a self-test fails.

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patent: 5504684 (1996-04-01), Lau et al.
patent: 5592173 (1997-01-01), Lau et al.
patent: 5594874 (1997-01-01), Narayanan et al.

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