Processor data memory address generator

Details Processor data memory address generator Processor data memory address generator

1991-09-19

1994-10-11

Dixon, Joseph L.

Boots, shoes, and leggings

395375, 395800, 364251, 3642551, 3642554, 3642558, 364DIG1, G06F 1200, G06F 926, G06F 934, G06F 1576

Patent

active

053554620

ABSTRACT:
A processor data memory address generator is adapted to receive a control word from a program controller receiving instructions from a program memory addressed by an instruction counter and producing a program signal addressed to an arithmetic and logic unit. The instruction counter is incremented by a clock signal and reset by the program controller. The control word comprises location information and selection information and the address generator is adapted to produce a data address having a first part comprising bits of said location information and a second part formed by a selected set of bits of the address of the current instruction identified by said selection information.

REFERENCES:
patent: 4202035 (1980-05-01), Lane
patent: 4521858 (1985-06-01), Kraemer et al.
patent: 4833602 (1989-05-01), Levy et al.
patent: 4908748 (1990-03-01), Pathak et al.
patent: 4935867 (1990-06-01), Wang et al.
patent: 5032986 (1991-07-01), Pathak et al.
"General Addressing Mechanisms For Microprocessors" by Gordon Steven and Fleur Williams, Microprocessors and Microsystems, vol. 12, No. 2, Mar. 1988, pp. 67-75.

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