Processor cycle tracking in a controller for two-way set associa

Details Processor cycle tracking in a controller for two-way set associa Processor cycle tracking in a controller for two-way set associa

1994-03-01

1995-02-21

Elmore, Reba I.

Boots, shoes, and leggings

364DIG1, 36424341, G06F 1208

Patent

active

053924177

ABSTRACT:
A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag random access memory (tag RAM). Internal cycles are tracked by a first logic in the tag RAM that responds to an external cycle (EXCYC) signal and asserts an internal cycle (INCYC) signal during a time when a request to the tag RAM is pending. A second logic combines the INCYC signal with the. ADS to generate an address strobe wait (ADSWAIT) signal. A third logic combines the ADSWAIT signal with the ADS to generate an address strobe cycle (ADSCYC) signal. A fourth logic responsive to one of several end-of-cycle signals generates a terminate signal to signify an end of a current cycle. A fifth logic asserts the EXCYC signal in response to the ADSCYC signal and unasserts the EXCYC signal in response to the terminate signal.

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