Processor controlled telecommunication switching system

Details Processor controlled telecommunication switching system Processor controlled telecommunication switching system

1974-09-23

1980-06-10

Brown, Thomas W.

H04Q 354

Patent

active

042074371

ABSTRACT:
Each memory individually associated with a respective one of two processors of a centrally controlled switching system incorporates status buffers. Information relating to each call is stored in a pair of status buffers in each memory, the status buffers of each pair being interlinked by linkage information. In case of a partial or a total breakdown of the system without the memory of at least one processor being affected, a special recovery program is executed by the latter processor to clear not only all the calls which are not in conversation, or not in a supervision phase, but also all the calls in a conversation phase for which pairs of associated status buffers contain erroneous linkage information.

REFERENCES:
patent: 3838261 (1974-09-01), Rice et al.
"Metaconta Switching System," pp. 223-245, Electrical Communication, vol. 46, No. 4, 1971.

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