Processor controlled interface with instruction streaming

Details Processor controlled interface with instruction streaming Processor controlled interface with instruction streaming

1988-10-11

1991-06-25

Eng, David Y.

Boots, shoes, and leggings

3642434, 36424341, G06F 1212, G06F 1300

Patent

active

050272705

ABSTRACT:
A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.

REFERENCES:
patent: 3967247 (1976-06-01), Andersen
patent: 4313158 (1982-01-01), Porter et al.
patent: 4502110 (1985-02-01), Saito
patent: 4622631 (1986-11-01), Frank et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4847758 (1989-07-01), Olson et al.

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