Boots – shoes – and leggings
Patent
1993-12-23
1996-05-21
Bowler, Alyssa H.
Boots, shoes, and leggings
395401, 395402, 364DIG1, G06F 1200
Patent
active
055198767
ABSTRACT:
A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.
REFERENCES:
patent: 4644469 (1987-02-01), Sumi
patent: 4774652 (1988-09-01), Dhuey et al.
patent: 4807196 (1989-02-01), Mizukami
patent: 4855581 (1989-08-01), Mertel et al.
patent: 4947366 (1990-08-01), Johnson
patent: 5012468 (1991-04-01), Siegel et al.
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5109490 (1992-04-01), Arimilli
patent: 5210834 (1993-05-01), Zurawski et al.
patent: 5237567 (1993-08-01), Nay et al.
patent: 5245705 (1993-09-01), Swaney
patent: 5287460 (1994-02-01), Olsen et al.
patent: 5384789 (1995-01-01), Tomita
Byers Larry L.
De Subijana Joseba M.
Michaelson Wayne A.
Bowler Alyssa H.
Johnson Charles A.
Nguyen Dzung C.
Skabrat Steven P.
Starr Mark T.
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