Processor communication bus

Details Processor communication bus Processor communication bus

1990-10-31

1993-08-17

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 852, 370 856, 370 857, 370 8511, H04J 302

Patent

active

052375676

ABSTRACT:
In a computer system that contains plural computer resource elements, such as multiple processor and memory units, with those elements communicating digital information over a common communications bus, high communications bus efficiency is achieved. An interface permits each of said processor and memory elements to individually and independently access either the data bus, without busying the address bus, or the address bus without busying the data bus, with bus access being limited to a fixed interval of time. Different ones of said processor and memory units may thus simultaneously transfer digital information over the respective address and data bus. The foregoing system includes a bus contention and priority protocol to eliminate the possibility of data collision and includes identification lines for identifying each processor element accessing the bus.

REFERENCES:
patent: 4229792 (1980-10-01), Jensen et al.
patent: 4550402 (1985-10-01), Gable et al.
patent: 4604743 (1986-08-01), Alexandru

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