Processor cluster architecture and associated parallel...

Details Processor cluster architecture and associated parallel... Processor cluster architecture and associated parallel...

2006-08-31

2010-11-23

Kindred, Alford W (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S010000

Reexamination Certificate

active

07840778

ABSTRACT:
A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

REFERENCES:
patent: 3537074 (1970-10-01), Sankin et al.
patent: 4351025 (1982-09-01), Hall, Jr.
patent: 4571672 (1986-02-01), Hatada et al.
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 4943912 (1990-07-01), Aoyama et al.
patent: 5121498 (1992-06-01), Gilbert et al.
patent: 5303369 (1994-04-01), Borcherding et al.
patent: 5586258 (1996-12-01), Conterno et al.
patent: 5734921 (1998-03-01), Dapp et al.
patent: 5752264 (1998-05-01), Blake et al.
patent: 5832216 (1998-11-01), Szczepanek
patent: 5857084 (1999-01-01), Klein
patent: 5881254 (1999-03-01), Corrigan et al.
patent: 5941973 (1999-08-01), Kondo et al.
patent: 6041379 (2000-03-01), Sher
patent: 6052752 (2000-04-01), Kwon
patent: 6055599 (2000-04-01), Han et al.
patent: 6092173 (2000-07-01), Sasaki et al.
patent: 6131153 (2000-10-01), Takamatsu
patent: 6151663 (2000-11-01), Pawlowski et al.
patent: 6167475 (2000-12-01), Carr
patent: 6205522 (2001-03-01), Hudson et al.
patent: 6212589 (2001-04-01), Hayek et al.
patent: 6338122 (2002-01-01), Baumgartner et al.
patent: 6339788 (2002-01-01), Geyer et al.
patent: 6351781 (2002-02-01), Gracias et al.
patent: 6393500 (2002-05-01), Thekkath
patent: 6493776 (2002-12-01), Coutright et al.
patent: 6502150 (2002-12-01), Bogin et al.
patent: 6526462 (2003-02-01), Elabd
patent: 6598130 (2003-07-01), Harris et al.
patent: 6604159 (2003-08-01), Thekkath et al.
patent: 6622214 (2003-09-01), Vogt et al.
patent: 6628662 (2003-09-01), Blackmon et al.
patent: 6631447 (2003-10-01), Morioka et al.
patent: 6636950 (2003-10-01), Mithal et al.
patent: RE38388 (2004-01-01), Sarangdhar et al.
patent: 6704842 (2004-03-01), Janakiraman et al.
patent: 6721833 (2004-04-01), Lai et al.
patent: 6738845 (2004-05-01), Hadwiger et al.
patent: 6748505 (2004-06-01), Dakhil
patent: 6785793 (2004-08-01), Aboulenein et al.
patent: 6799254 (2004-09-01), Oldfield et al.
patent: 6813767 (2004-11-01), Wilke
patent: 6842845 (2005-01-01), Ganapathy et al.
patent: 6892266 (2005-05-01), Reimer et al.
patent: 6920519 (2005-07-01), Beukema et al.
patent: 6959372 (2005-10-01), Hobson et al.
patent: 7085866 (2006-08-01), Hobson et al.
patent: 7107383 (2006-09-01), Rajan
patent: 7174401 (2007-02-01), Stuber et al.
patent: 7210139 (2007-04-01), Hobson et al.
patent: 7469308 (2008-12-01), Hobson et al.
patent: 2001/0003834 (2001-06-01), Shimonishi
patent: 2001/0046237 (2001-11-01), Chan et al.
patent: 2001/0054079 (2001-12-01), Hagersten et al.
patent: 2002/0004886 (2002-01-01), Hagersten et al.
patent: 2002/0052914 (2002-05-01), Zalewski et al.
patent: 2002/0083243 (2002-06-01), Van Huben et al.
patent: 2002/0157035 (2002-10-01), Wong et al.
patent: 2002/0194435 (2002-12-01), Yamagami et al.
patent: 2003/0097530 (2003-05-01), Arimilli et al.
patent: 2004/0103263 (2004-05-01), Colavin et al.
patent: 2005/0033941 (2005-02-01), Joyce et al.
patent: 2009/0106468 (2009-04-01), Hobson et al.

Affiliated with

Also associated with

Rating

Processor cluster architecture and associated parallel... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor cluster architecture and associated parallel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor cluster architecture and associated parallel... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4190978