Processor cluster architecture and associated parallel...

Details Processor cluster architecture and associated parallel... Processor cluster architecture and associated parallel...

2007-04-24

2007-04-24

Peugh, Brian R. (Department: 2187)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C712S213000

Reexamination Certificate

active

11255597

ABSTRACT:
A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

REFERENCES:
patent: 3537074 (1970-10-01), Sankin et al.
patent: 5121498 (1992-06-01), Gilbert et al.
patent: 2005/0033941 (2005-02-01), Joyce et al.

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