Processor circuits, systems, and methods with efficient...

Details Processor circuits, systems, and methods with efficient... Processor circuits, systems, and methods with efficient...

1999-10-29

2002-08-06

Pan, Daniel H. (Department: 2783)

Electrical computers and digital processing systems: processing

Byte-word rearranging, bit-field insertion or extraction,...

C712S225000, C712S224000, C712S223000, C711S219000, C711S212000, C711S220000, C711S214000, C708S209000, C708S490000, C710S065000, C710S066000, C710S068000, C710S120000, C714S712000

Reexamination Certificate

active

06430684

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to processors, and are more particularly directed to improving the availability and implementation of three operand shift and/or merge instructions and operations in such processors.
The present embodiments pertain to the ever-evolving fields of computer technology, microprocessors, and other types of processors. Processor devices are used in numerous applications, and their prevalence has led to a complex and demanding marketplace where efficiency of operation is often a key consideration, where such efficiency is reflected in price and performance of the processor. The following discussion and embodiments are directed to processor efficiency and functionality, and arise in the area of shift-merge instruction capability.
The prior art includes a number of bit manipulation instructions where each such instruction is implemented in certain processors because it permits data to be manipulated using a single instruction, whereas if the instruction is not part of the processor instruction set the same resulting data manipulation may require considerably more than one instruction. To demonstrate these types of instructions, four different examples are provided below. Before detailing those instructions,
FIG. 1
introduces the basic instruction format of all of these instructions via a general instruction
10
. Instruction
10
includes an opcode, which includes a number of bits forming a unique bit pattern which defines the specific type of instruction. Instruction
10
further includes references to two data operands, shown as data D
1
and data D
2
. These references are commonly to corresponding registers and it is not intended therefore to demonstrate that these data are directly embedded in instruction
10
. Additionally, for the sake of discussion and as a contemporary example, data D
1
and D
2
are typically 32-bit quantities stored in the registers and often there are 32 such registers; as a result, the references to data D
1
and D
2
are 5-bit identifiers which each identify a corresponding one of the 32 registers in which either data D
1
or data D
2
is stored. Instruction
10
also includes one or more bit manipulation arguments where for the examples provided below there is either two 5-bit arguments for a total of 10 bits, or a single 5-bit argument. Different arguments are discussed below based on a particular corresponding instruction, but typically the arguments relate to some parameter for manipulating data D
1
and D
2
such as a shift amount, a position, or a number of bits to be manipulated. As explored in more detail below, note that the argument(s) may be either immediate information (i.e., embedded within instruction
10
) or addressed by the instruction so that they are read from a storage device (e.g., register). Finally, note that instruction
10
also includes a destination reference DEST, where this reference is also commonly to one of 32 registers and, hence, is also a five bit identifier. The DEST location is the register where the result of the operation of instruction
10
is written.
FIGS. 2
a
and
2
b
illustrate the operands and operation of a prior art INSERT instruction.
FIG. 2
a
illustrates the two 32-bit data operands of the INSERT instruction, and which are shown as data A and B. The third operand of an INSERT instruction is a bit manipulation operand which provides two aspects, and in this regard is typically embodied as a 10-bit operand, where five of these bits define a SHIFT argument and the remaining five of these bits define a LENGTH argument. The SHIFT argument defines the number of bits that data A is to be right shifted, that is, shifted so that its most significant bit is shifted towards the original position of its least significant bit. Thus,
FIG. 2
a
illustrates the right shifting of data A in response to the SHIFT argument by way of a right-pointing arrow, with the result following the shift being designated as A
S
in
FIG. 2
b
. For example, if SHIFT equals six, then data A is shifted right by six bits with the result, A
S
, starting at its least significant bit, having the 26 more significant bits from data A. Note that A
S
is shown in
FIG. 2
b
only to demonstrate the functionality of the shift, and is not intended to suggest that an additional storage device or clock cycle is required to temporarily store the shifted value A
S
. The LENGTH argument defines the number of bits that are taken from A
S
(i.e., the shifted value of A) and copied over the value of data B starting at the least significant bit of data B; for sake of reference, the LENGTH number of bits from A
S
and copied in this manner are shown as A
SL
. Thus,
FIG. 2
b
illustrates that a number of bits equal to LENGTH from A
S
are copied over data B, thereby creating a result R
1
which includes a value A
SL
starting at bit
0
and continuing up to bit LENGTH−1. The remaining bits in result R
1
are identical to the corresponding bit locations from data B. Given the preceding, it may be stated that a number of bits equal to LENGTH from A
S
are merged with data B and, thus, this is why the INSERT ins is a type of shift-merge instruction.
FIGS. 3
a
and
3
b
illustrate the operands and operation of a prior art DEPOSIT instruction.
FIG. 3
a
illustrates the two 32-bit data operands of the DEPOSIT instruction, and which are shown as data C and D. The third operand of the DEPOSIT instruction is a bit manipulation operand which provides two aspects and also is typically embodied as a 10-bit operand, where five of these bits define a SHIFT argument and the remaining five of these bits define a LENGTH argument. The SHIFT argument defines the number of bits that data C is to be left shifted, that is, shifted so that its least significant bit is shifted towards the original location of its most significant bit. Thus,
FIG. 3
a
illustrates the left shifting in response to the SHIFT argument by way of a left-pointing arrow, with the result following the shift being designated as C
S
in
FIG. 3
b
. For example, if SHIFT equals four, then data C is shifted left by four bits with the result, C
S
, starting at its least significant bit, having the 28 least significant bits from data C. Note that C
S
is shown in
FIG. 3
b
only to demonstrate the functionality of the shift, and is not intended to suggest that an additional storage device or clock cycle is required to temporarily store the shifted value C
S
. The LENGTH argument defines the number of bits that are taken from C
S
(i.e., the shifted value of C) and copied over or “merged with” the value of data D starting at bit location SHIFT and continuing, therefore, up to bit location SHIFT+LENGTH−1; for sake of reference, the LENGTH number of bits from C
S
are shown as C
SL
. Thus,
FIG. 3
b
illustrates that C
SL
is copied over the corresponding bit locations in data D, thereby creating a result R
2
which includes a value C
SL
starting at bit SHIFT and continuing up to bit SHIFT+LENGTH−1. The remaining bits in result R
3
are identical to the corresponding bit locations from data C, and appear in both the upper and lower bit locations of result R
2
(assuming SHIFT is greater than zero and less than 32).
FIGS. 4
a
and
4
b
illustrate the operands and operation of a prior art REPLACE instruction.
FIG. 4
a
illustrates the two 32-bit data operands of the REPLACE instruction, and which are shown as data E and F. The third operand of the REPLACE instruction is a bit manipulation operand which provides two aspects and also is typically embodied as a 10-bit operand, where five of these bits define a POSITION argument and the remaining five of these bits define a LENGTH argument. The POSITION argument defines a bit position in data E, and the LENGTH argument defines a number of bits that are copied from data E starting at the POSITION bit. More particularly, these copied bits form a quantity shown in
FIG. 4
b
as E
L
, and they are copied

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