Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1998-03-03
2002-10-22
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000
Reexamination Certificate
active
06470376
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor to be used in an AV (Audio Visual) decoder that reproduces multimedia data of variable code length, such as MPEG (Moving Pictures Experts Group) streams, and is a specialized processor that oversees the periphery control by the main processor in an AV decoder.
2. Description of the Prior Art
The reproduction of MPEG streams is a fundamental technique in the field of multimedia and has been subject to an explosion in demand in recent years. Of the various MPEG reproduction techniques, the new field of consumer reproduction devices that interactively reproduce video and audio has been subject to special attention. To ensure the success of their products, the various manufacturers in this field have been making huge efforts to develop AV decoders that enable the high quality reproduction of MPEG streams.
While a variety of processes are necessary when reproducing MPEG streams, these processes can be roughly classified into Audio-Video (AV) decoding core processing and asynchronous event processing.
The AV decoding core processing for MPEG reproduction is composed of processes such as inverse quantization, inverse discrete cosine transform (hereinafter, “DCT”), and motion compensation that are performed on macro blocks composed of 16 by 16 pixels. Since 4,050 (=30 frames*30 slices*45 macro blocks) macro blocks need to be processed every second, a huge amount of computation is required. The execution of the AV decoding core processing is well suited to pipeline processing, and when increases in the scale of the hardware are not a concern, a plurality of decoders and calculators can be provided to share the load of the AV decoding core processing.
The asynchronous event processing is composed of processing that should be intensively executed when a certain state (hereinafter, “phenomenon”) is present due to the concurrence of a plurality of factors, and processing that should be cyclically performed with a given interval. In short, asynchronous event processing is a general name for processing that cannot be performed in synchronization with the AV decoding core processing.
For an AV decoder, the processing which corresponds to this asynchronous event processing has the following three types.
(1) Processing relating to input of MPEG streams from a recording medium or a communication medium.
(2) Processing relating to output from the AV decoder to an image reproduction device and an audio reproduction device.
(3) Processing relating to input and output between the AV decoder and an expansion memory provided externally to the AV decoder.
Of these, the asynchronous event processing (1) related to the input of streams from a recording medium includes (1-1) extraction processing whereby elementary streams are extracted from the MPEG streams taken from a recording medium such as an optical disc, or a communication medium, and (1-2) write processing whereby the extracted elementary streams are written into an SDRAM connected as an expansion memory.
The asynchronous event processing (2) related to output and reproduction includes (2-1) output processing whereby video streams and audio streams are decoded into video signals and audio signals and are outputted to a display and speakers, and (2-2) processing whereby sub-pictures outputted as the private stream in the MPEG stream are formed and combined with the video data to superimpose subtitles onto the image signal.
The asynchronous event processing (3) related to input and output between the AV decoder and the expansion memory includes (3-1) write processing whereby the accumulation of data that has been subjected to inverse quantization, inverse DCT, and motion compensation in the internal buffer is monitored until a certain amount of data has been reached, at which point the data is collectively written into the SDRAM, and (3-2) replenish processing whereby the internal buffer is intermittently replenished with unprocessed data from the externally connected SDRAM as the inverse quantization, inverse DCT, and motion compensation progress.
In addition to the kinds of processing described above, processing which needs to be performed in response to user operations is also classified as asynchronous event processing. For application systems where reproduction apparatuses not only reproduce MPEG streams but also allow the user to make interactive operations, or systems where control is performed in synchronization with a host computer, there is a greater need for such asynchronous event processing to be performed by the AV decoder.
Of the kinds of processing described above, processing (2-1) includes processing known as “audio out tasks” and is performed at intervals of 90 &mgr;sec, and processing known as “video out tasks” where the processing of one line of images needs to be completed within 50 &mgr;sec based on the interval of the horizontal synchronization signal of a display.
The reason the audio out tasks and video out tasks described above are given the execution cycles described above is that these tasks need to be completed within the given time for smooth, real-time reproduction of video and audio to be possible. This is to say, the completion of video out tasks and audio out tasks within the stated 50 &mgr;sec and 90 &mgr;sec cycles is the principle requirement for video and audio reproduction to be performed in real time.
Under conventional MPEG stream reproduction techniques, when asynchronous event processing is to be performed by a standard processor, the processor is informed of the appearance of the certain phenomenon for the asynchronous event or of the elapsing of the stipulated interval. Having been informed that asynchronous event processing is to be performed, the standard processor uses a branch instruction to branch to the asynchronous event processing.
However, under conventional methods where asynchronous event processing is executed by standard processor using an interrupt signal, there is the problem that there is no universal method for calculating the optimal minimum operation clock frequency which shows the minimum setting of the operation clock required for the processing of audio out tasks and video out tasks to be completed on time.
Since there is no way of calculating the optimal minimum number, the operation clock has to be determined by making a generous estimate, so that there is a general tendancy for the operation clock frequency to be set too high.
The following is a description of the conventional calculation method used for calculating the operation clock. This description will focus on the case where processing with different intervals, which is to say audio out tasks with an execution interval of 90 &mgr;sec and video out tasks with an execution interval of 50 &mgr;sec have to be executed. In this case, the decoding of audio streams needs to be completed at 90 &mgr;sec intervals, which is to say by the 0 &mgr;sec, 90 &mgr;sec, 180 &mgr;sec, 270 &mgr;sec, 360 &mgr;sec, and 450 &mgr;sec marks, while the decoding of video streams needs to be completed at 50 &mgr;sec intervals, which is to say by the 0 &mgr;sec, 50 &mgr;sec, 100 &mgr;sec, 150 &mgr;sec, 200 &mgr;sec, and 250 &mgr;sec marks. Here, a conventional processor is informed of the elapsing of the two intervals by interrupt signals and then processes the video out tasks and audio out tasks.
On being informed of the time to execute by an interrupt signal and activating the video out task and audio out tasks, the time limit for completing the processing of each task is found as the time from the occurrence of the interrupt signal for activating the processor to the time at which the interrupt signal for activating the next task is issued.
FIG. 1
is a timing chart showing the case when a standard processor executes the tasks described above having been informed by the interrupt signals with the stated intervals of 50 &mgr;sec and 90 &mgr;sec. The following is an explanation of the time limits for the completion of the audio out tasks and vid
Hirai Makoto
Kiyohara Tokuzo
Maenobu Kiyoshi
Tanaka Takaharu
Yoshioka Kosuke
Donaghue Larry D.
Matsushita Electric Industrial Co. LTD
Price & Gess
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