1991-10-04
1994-08-23
Shaw, Dale M.
395325, G06F 946
Patent
active
053415019
ABSTRACT:
A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
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Keeley James W.
Lemay Richard A.
Nibby, Jr. Chester M.
Bull HN Information Systems Inc.
Driscoll Faith F.
Meky Moustafa M.
Shaw Dale M.
Solakian John S.
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