Processor board having a second level writeback cache system and

Details Processor board having a second level writeback cache system and Processor board having a second level writeback cache system and

1994-05-04

1996-10-01

Kim, Matthew M.

Boots, shoes, and leggings

395457, 395469, 395470, 395471, 395472, 395473, 364DIG1, 36424345, G06F 1208

Patent

active

055617794

ABSTRACT:
A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache. However, the shared or exclusive status of any cached data is also stored. If the second level cache performs a write allocate cycle and the data is exclusive in the third level cache, the data is provided directly from the third level cache, without requiring an access to main memory, reducing the use of the host bus.

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Mori et al., A Distributed Shared Memory Multiprocessor: Asura-Memory And Cache Architectures-, Proceedings Supercomputing '93, Nov. 15, 1993, pp. 740-749.

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