Processor array with relocated operand physical address generato

Details Processor array with relocated operand physical address generato Processor array with relocated operand physical address generato

1990-05-29

1993-03-09

Anderson, Lawrence E.

Boots, shoes, and leggings

3642319, 3642282, 3642321, 3642457, 3642555, 3642566, 3642621, 36493101, 36493146, 3649468, 3649467, 3642612, 3649551, 3649612, 364DIG1, 395375, 395400, G06F 1580, G06F 1206

Patent

active

051932024

ABSTRACT:
A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than the number of nodes in the problem space. The system partitions the memory of each physical processor cell into several equal sections, each section being associated with one node of the problem space. The instruction generator then produces a sequence of processor cell instructions for each node of the given problem space, with appropriate address modifications for each sequence of instructions provided by an address relocation circuit.

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