Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2004-01-26
2009-08-11
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S018000, C712S031000
Reexamination Certificate
active
07574582
ABSTRACT:
There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while communications to and from closer array elements are deliberately “over-pipelined” such that the latency to all end-point elements is the same number of clock cycles. The processor array has a plurality of primary buses, each connected to a primary bus driver, and each having a respective plurality of primary bus nodes thereon; respective pluralities of secondary buses, connected to said primary bus nodes; a plurality of processor elements, each connected to one of the secondary buses; and delay elements associated with the primary bus nodes, for delaying communications with processor elements connected to different ones of the secondary buses by different amounts, in order to achieve a degree of synchronization between operation of said processor elements.
REFERENCES:
patent: 4380046 (1983-04-01), Frosch et al.
patent: 4574345 (1986-03-01), Konesky
patent: 4622632 (1986-11-01), Tanimoto et al.
patent: 4720780 (1988-01-01), Dolecek
patent: 4736291 (1988-04-01), Jennings et al.
patent: 4814970 (1989-03-01), Barbagelata et al.
patent: 4825359 (1989-04-01), Ohkami et al.
patent: 4890279 (1989-12-01), Lubarsky
patent: 4943912 (1990-07-01), Aoyama et al.
patent: 4992933 (1991-02-01), Taylor
patent: 5036453 (1991-07-01), Renner et al.
patent: 5109329 (1992-04-01), Strelioff
patent: 5152000 (1992-09-01), Hillis
patent: 5265207 (1993-11-01), Zak et al.
patent: 5384697 (1995-01-01), Pascucci
patent: 5570045 (1996-10-01), Erdal et al.
patent: 5719445 (1998-02-01), McClure
patent: 5752067 (1998-05-01), Wilkinson et al.
patent: 5790879 (1998-08-01), Wu
patent: 5805839 (1998-09-01), Singhal
patent: 6052752 (2000-04-01), Kwon
patent: 6122677 (2000-09-01), Porterfield
patent: 6175665 (2001-01-01), Sawada
patent: 6393026 (2002-05-01), Irwin
patent: 6928500 (2005-08-01), Ramanujan et al.
patent: A-8-297652 (1996-11-01), None
patent: 2 370 380 (2002-06-01), None
patent: WO 02/50624 (2002-06-01), None
patent: WO 02/50624 (2002-06-01), None
Kober, Rudolf, “Multiprocessor System SMS 201—Combining 128 Microprocessors to a Powerful Computer,” Sep. 1977, Compcon '77, pp. 225-230.
Knight, Thomas and Wu, Henry, “A Method for Skew-free Distribution of Digital Signals using Matched Variable Delay Lines,” VLSI Circuits, 1993. Digest of Techinical Papers. 1993 Symposium on, May 1993, pp. 19-21.
Hierarchical multiprocessor organizations; J. Archer Harris; David R. Smith ; International Symposium on Computer Architecture ;Proceedings of the 4th annual symposium on Computer architecture pp. 41-48 Year of Publication: 1977.
“Hierarchical Interconnection Networks for Multicomputer Systems” Sivarama P. Dandamudi et. al. IEEE Transactions on Computers archive vol. 39 , Issue 6 (Jun. 1990)pp. 786-797 Year of Publication: 1990.
A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems Wu, S.B. Liu, M.T. This paper appears in: Transactions on Computers Publication Date: Apr. 1981 vol. C-30, Issue: 4 On pp. 254-264.
Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors S. M. Mahmud IEEE Transactions on Computers archive vol. 43 , Issue 7 (Jul. 1994) pp. 789-805 Year of Publication: 1994.
Performance Analysis of a Generalized Class of M-Level Hierarchical Multiprocessor Systems I.O. Mahgoub A.K. Elmagarmid Mar. 1992 (vol. 3, No. 2) pp. 129-138.
“Data management in hierarchical bus networks” F. Meyer auf der Heide et al.; ACM Symposium on Parallel Algorithms and Architectures, Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures, pp. 109-118 Year of Publication: 2000.
Written Opinion and International Search Report of PCT/GB2004/000255 dated Mar. 22, 2004.
Chan Eddie P
Picochip Designs Limited
Potomac Patent Group PLLC
Vicary Keith
LandOfFree
Processor array including delay elements associated with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor array including delay elements associated with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor array including delay elements associated with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4116331