Processor array comprising processors connected selectively in s

Details Processor array comprising processors connected selectively in s Processor array comprising processors connected selectively in s

1990-01-17

1991-05-07

Shaw, Gareth D.

Boots, shoes, and leggings

3642294, 3642319, 3642327, G06F 1580, G06F 1516

Patent

active

050141899

ABSTRACT:
A processor array has first through N-th processor. Each of first through (N-1)-th switching devices is connected between preceding and succeeding consecutively numbered ones of the first through the N-th processors. Each processor has at least one processor module coupled between a processor input bus and a processor output bus. A controlling unit controls the switching devices so that the input and output buses of the processor are selectively connected together. Each processor includes a feedback bus which is connected to the module. The (N-1)-th switching devices are controlled so that the feedback buses of the processor are selectively connected in series in compliance with the manner in which the processor input and output buses of the processors are connected together. The controlling unit may also control the processor modules of each processor. The processor modules of one or more processors may process partial blocks of each principal block of a digital video signal, respectively, throughout a time duration of the principal block. The control unit may put the processor modules into operation either only one in each time duration or repeatedly in a time division fashion.

REFERENCES:
patent: 4384273 (1983-05-01), Ackland et al.
patent: 4542455 (1985-09-01), Demeure
patent: 4574345 (1986-03-01), Konesky
patent: 4707833 (1987-11-01), Tamara

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