Processor array accessing data in memory array coupled to...

Details Processor array accessing data in memory array coupled to... Processor array accessing data in memory array coupled to...

2007-05-16

2011-12-13

Kim, Kenneth (Department: 2111)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S225000

Reexamination Certificate

active

08078830

ABSTRACT:
An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.

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Kyo, S., et al; “An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems”; Computer Architecture, 2005; ISCA 2005; IEEE Jun. 4, 2005; pp. 134-145; XP010807901.
Hsieh, J.Y.F., et al; “Tranpose Memory for Video Rate JPEG Compression on Highly Parallel Single-Chip Digital CMOS Imager”; Image Processing 2000; 2000 International Conference, Sep. 10-13, 2000, Piscataway, NJ, USA, IEEE; Sep. 10, 2000; pp. 102-105; XP01059413.

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