Processor array

Details Processor array Processor array

1996-03-01

1998-09-29

Tsai, Jey

Static information storage and retrieval

Magnetic bubbles

Guide structure

36523005, 438128, G06F 1300

Patent

active

058157280

ABSTRACT:
A processor array 100 having an improved I/O pin utilization scheme. The inventive processor array 100 includes a first and a second set of processors 112 and 114 arranged within a chip boundary B1, with each of the processors 112 within the first set being positioned adjacent the chip boundary B1. The invention further includes an I/O arrangement for providing a plurality of electrical paths 136 across the chip boundary B1. A switch network is included for connecting each of the I/O paths 136 to a horizontal port 130 of an associated one of the processors 112 within the first set during a first clock cycle and for connecting each of the I/O paths 136 to a vertical communication port 132 of the associated processor during a second clock cycle.

REFERENCES:
patent: 5212773 (1993-05-01), Hillis
patent: 5410723 (1995-04-01), Schmidt et al.
patent: 5581767 (1996-12-01), Katsuki et al.

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