Processor architecture with wide operand cache

Computer graphics processing and selective visual display system – Computer graphic processing system – Graphic command processing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S001000, C712S220000, C712S225000

Reexamination Certificate

active

07948496

ABSTRACT:
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

REFERENCES:
patent: 3581279 (1971-05-01), Arbuckle
patent: 3833889 (1974-09-01), Cray
patent: 4251875 (1981-02-01), Marver et al.
patent: 4393468 (1983-07-01), New
patent: 4658349 (1987-04-01), Tabata et al.
patent: 4658908 (1987-04-01), Hannukainen
patent: 4785393 (1988-11-01), Chu et al.
patent: 4823259 (1989-04-01), Aichelmann et al.
patent: 4930106 (1990-05-01), Danilenko et al.
patent: 5031135 (1991-07-01), Patel et al.
patent: 5170399 (1992-12-01), Cameron et al.
patent: 5185861 (1993-02-01), Valencia
patent: 5280598 (1994-01-01), Osaki et al.
patent: 5283886 (1994-02-01), Nishii et al.
patent: 5325493 (1994-06-01), Herrell et al.
patent: 5333280 (1994-07-01), Ishikawa et al.
patent: 5375215 (1994-12-01), Hanawa et al.
patent: 5426379 (1995-06-01), Trimberger
patent: 5430556 (1995-07-01), Ito
patent: 5471593 (1995-11-01), Branigin
patent: 5481686 (1996-01-01), Dockser
patent: 5487024 (1996-01-01), Girardeau, Jr.
patent: 5509137 (1996-04-01), Itomitsu et al.
patent: 5535225 (1996-07-01), Mayhew et al.
patent: 5550988 (1996-08-01), Sarangdhar et al.
patent: 5551005 (1996-08-01), Sarangdhar et al.
patent: 5579253 (1996-11-01), Lee et al.
patent: 5598362 (1997-01-01), Adelman et al.
patent: 5600814 (1997-02-01), Gahan et al.
patent: 5604864 (1997-02-01), Noda
patent: 5636363 (1997-06-01), Bourekas et al.
patent: 5646626 (1997-07-01), Willis
patent: 5669012 (1997-09-01), Shimizu et al.
patent: 5671170 (1997-09-01), Markstein et al.
patent: 5675526 (1997-10-01), Peleg et al.
patent: 5717946 (1998-02-01), Satou et al.
patent: 5721892 (1998-02-01), Peleg et al.
patent: 5740093 (1998-04-01), Sharangpani
patent: 5742840 (1998-04-01), Hansen et al.
patent: 5745729 (1998-04-01), Greenley et al.
patent: 5745778 (1998-04-01), Alfieri
patent: 5752001 (1998-05-01), Dulong
patent: 5752264 (1998-05-01), Blake et al.
patent: 5765216 (1998-06-01), Weng et al.
patent: 5768546 (1998-06-01), Kwon
patent: 5778412 (1998-07-01), Gafken
patent: 5799165 (1998-08-01), Favor et al.
patent: 5802336 (1998-09-01), Peleg et al.
patent: 5826079 (1998-10-01), Boland et al.
patent: 5826081 (1998-10-01), Zolnowsky
patent: 5835744 (1998-11-01), Tran et al.
patent: 5835782 (1998-11-01), Lin et al.
patent: 5835968 (1998-11-01), Mahalingaiah et al.
patent: 5872972 (1999-02-01), Boland et al.
patent: 5889983 (1999-03-01), Mittal et al.
patent: 5933650 (1999-08-01), van Hook et al.
patent: 5935240 (1999-08-01), Mennemeier et al.
patent: 5940859 (1999-08-01), Bistry et al.
patent: 5991531 (1999-11-01), Song et al.
patent: 5999959 (1999-12-01), Weng et al.
patent: 6006299 (1999-12-01), Wang et al.
patent: 6038675 (2000-03-01), Gabzdyl et al.
patent: 6041404 (2000-03-01), Roussel et al.
patent: 6058408 (2000-05-01), Fischer et al.
patent: 6061780 (2000-05-01), Shippy et al.
patent: 6105053 (2000-08-01), Kimmel et al.
patent: 6131145 (2000-10-01), Matsubara et al.
patent: 6134635 (2000-10-01), Reams
patent: 6141384 (2000-10-01), Wittig et al.
patent: 6141675 (2000-10-01), Slavenburg et al.
patent: 6211892 (2001-04-01), Huff et al.
patent: 6212618 (2001-04-01), Roussel
patent: 6237016 (2001-05-01), Fischer et al.
patent: 6243803 (2001-06-01), Abdallah et al.
patent: 6263428 (2001-07-01), Nonomura et al.
patent: 6266758 (2001-07-01), Van Hook et al.
patent: 6269390 (2001-07-01), Boland
patent: 6292815 (2001-09-01), Abdallah et al.
patent: 6295599 (2001-09-01), Hansen et al.
patent: 6317824 (2001-11-01), Thakkar et al.
patent: 6370559 (2002-04-01), Hoffman
patent: 6377970 (2002-04-01), Abdallah et al.
patent: 6378060 (2002-04-01), Hansen et al.
patent: 6385634 (2002-05-01), Peleg et al.
patent: 6408325 (2002-06-01), Shaylor
patent: 6418529 (2002-07-01), Roussel
patent: 6426746 (2002-07-01), Hsieh et al.
patent: 6438660 (2002-08-01), Reams
patent: 6453368 (2002-09-01), Yamamoto
patent: 6463525 (2002-10-01), Prabhu
patent: 6470370 (2002-10-01), Fischer et al.
patent: 6516406 (2003-02-01), Peleg et al.
patent: 6567908 (2003-05-01), Furuhashi
patent: 6631389 (2003-10-01), Lin et al.
patent: 6633897 (2003-10-01), Browning et al.
patent: 6725356 (2004-04-01), Hansen et al.
patent: 6766515 (2004-07-01), Bitar et al.
patent: 6804766 (2004-10-01), Noel et al.
patent: 0651514 (1995-05-01), None
patent: 0800280 (1997-10-01), None
patent: 1024603 (2000-08-01), None
patent: 1102161 (2001-05-01), None
patent: 03-098145 (1991-04-01), None
patent: 06-149723 (1994-05-01), None
patent: 07-114496 (1995-05-01), None
patent: WO00/23875 (2000-04-01), None
U.S. Appl. No. 11/982,106 Office Action mailed on Feb. 3, 2010.
U.S. Appl. No. 11/982,124 Office Action mailed on Mar. 2, 2010.
U.S. Appl. No. 11/982,142 Notice of Allowance mailed on Mar. 12, 2010.
U.S. Appl. No. 11/346,213 Office Action mailed on Jan. 21, 2010.
Rice “Multiprecision Division on an 8-bit Processor”, Proceedings of the 13th IEEE Symposium on Computer Arithmetic, pp. 74-81 (Jul. 1997).
U.S. Appl. No. 11/982,230 Office Action mailed on Jun. 21, 2010.
U.S. Appl. No. 11/981,996 Office Action mailed on Nov. 27, 2009.
U.S. Appl. No. 11/982,230 Office Action mailed on Sep. 28, 2009.
U.S. Appl. No. 11/894,584 Office Action mailed on Nov. 10, 2009.
Hansen Architecture of a Broadband Mediaprocessor (1996) Proceedings of Compcon. New York, IEEE Computer Science, pp. 334-340 (1996).
Hansen “MicroUnity's MediaProcessor Architecture” IEEE Micro archive 16: 34-41 (Aug. 1996).
Japan Patent Office (JPO) office action for JPO patent application JP2005-107012 (Apr. 28, 2010).
U.S. Appl. No. 11/982,171 Office Action mailed on May 27, 2010.
Office Action in inter partes Reexamination 95/000100 (May 3, 2006).
Office Action in inter partes Reexamination 95/000100 (Mar. 19, 2009).
Right of Appeal Notice (37 CFR 1.953) in inter partes Reexamination 95/000100 (Jul. 11, 2009).
U.S. Appl. No. 11/982,106 Notice of Allowance mailed on Sep. 29, 2010.
U.S. Appl. No. 11/894,584 Office Action mailed on Sep. 16, 2010.
U.S. Appl. No. 11/981,996 Office Action mailed on Aug. 30, 2010.
U.S. Appl. No. 11/982,230 Office Action mailed on Sep. 27, 2010.
U.S. Appl. No. 11/982,124 Office Action mailed on Sep. 16, 2010.
U.S. Appl. No. 11/982,171 Office Action mailed on Sep. 8, 2010.
European Patent Office (EPO) search report for EPO patent application EP10160103.7 (Sep. 30, 2010).
GWENNAP “UltraSPARC Adds Multimedia Instructions,” Microprocessor Report, vol. 8, No. 6, pp. 1-3 (Dec. 5, 1994).
Hendrix “Viterbi Decoding Techniques in the TMS320C54x Family,” Texas Instruments, (Jan. 2002).
Lee “High-speed VLSI architecture for parallel Reed-Solomon decoder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11:288-294 (Apr. 2003).
Lee et al. “An efficient recursive cell architecture of modified Euclid's algorithm for decoding Reed-Solomon codes,” IEEE Transactions on Consumer Electronics 48:845-849 (Nov. 2002).
Leijten-Nowak et al. “An FPGA architecture with enhanced datapath functionality,” Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field Programmable Gate Arrays pp. 195-204 (Feb. 2003).
Sarwate et al. “High-speed architectures for Reed-Solomon decoders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9:641-655 (Oct. 2001).
European Search Report for application EP10167233

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Processor architecture with wide operand cache does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor architecture with wide operand cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor architecture with wide operand cache will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2627828

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.