Electrical computers and digital processing systems: processing – Instruction fetching – Of multiple instructions simultaneously
Reexamination Certificate
2006-10-17
2006-10-17
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Instruction fetching
Of multiple instructions simultaneously
Reexamination Certificate
active
07124282
ABSTRACT:
Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is started, the reading of one instruction which will be executed more than one instruction cycle later is also started. Consequently, a plurality of instructions are read in parallel from different memory banks. After the reading of an instruction, and before starting the execution of the instruction, the instruction passes through a pipeline in which the processing device detects whether the relevant instruction is a branch instruction. If this is so, the processing unit starts the reading in parallel of a number of instructions as from a branch target instruction. If it appears at a later stage that the branch is taken, said number of instructions is loaded into the pipeline in parallel.
REFERENCES:
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5261068 (1993-11-01), Gaskins et al.
patent: 5459843 (1995-10-01), Davis et al.
Vlot Marnix C.
Zandveld Frederik
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