Processor architecture scheme having multiple bank address overr

Details Processor architecture scheme having multiple bank address overr Processor architecture scheme having multiple bank address overr

1997-10-28

2000-02-22

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712 32, G06F 1206

Patent

active

060292415

ABSTRACT:
A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode. An instruction register is coupled to the selection circuit for supplying a bank address values for an instruction to be executed in a direct long addressing mode and for supplying a register address within a bank for the instruction to be executed in a direct short addressing mode.

REFERENCES:
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patent: 4118773 (1978-10-01), Joyce et al.
patent: 4685084 (1987-08-01), Canepa
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5751988 (1998-05-01), Fujimura

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