Processor architecture providing out-of-order execution

Details Processor architecture providing out-of-order execution Processor architecture providing out-of-order execution

1995-06-06

1997-05-06

Lim, Krisna

Boots, shoes, and leggings

3642318, 3642624, 3642629, 395394, G06F 930

Patent

active

056279833

ABSTRACT:
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

REFERENCES:
patent: 4325121 (1982-04-01), Gunter et al.
patent: 4338661 (1982-07-01), Tredennick et al.
patent: 4342078 (1982-07-01), Tredennick et al.
patent: 4402042 (1983-08-01), Guttag
patent: 4626989 (1986-12-01), Torii
patent: 4675806 (1987-06-01), Uchida
patent: 4722049 (1988-01-01), Lahti
patent: 4803615 (1989-02-01), Johnson
patent: 4807113 (1989-02-01), Matsumoto et al.
patent: 4807115 (1989-02-01), Torng
patent: 4811215 (1989-03-01), Smith
patent: 4926323 (1990-05-01), Baror et al.
patent: 5146570 (1992-09-01), Hester et al.
patent: 5226126 (1993-07-01), McFarland et al.
Sohi, G.S., "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1990.
Weiss, S., et al. "Instruction Issue Logic for Pipelined Supercomputers," IEEE, 1984.
Acosta et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions on Computers, 36(9):815-828 (1986).
Ramseyer et al., "A Multi-Microprocessor Implementation of a General Purpose Pipelined CPU," 4th Annual Symposium on Computer Architecture, pp. 29-34, Mar. 23, 1977.
Smith et al., "Implementing Precise Interrupts in Pipelined Computers," IEEE Transactions on Computers, 37(5):562-573 (1988).
Sohi, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," IEEE Transactions on Computers, 39(3):349-359 (1990).
Weiss et al., "Instruction Issue Logic for Pipelined Supercomputers," 11th Annual International Symposium on Computer Architecture, pp. 110-118, Jun. 5, 1984.

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