Processor architecture having independently fetching issuing and

Details Processor architecture having independently fetching issuing and Processor architecture having independently fetching issuing and

1990-12-05

1996-01-23

Lim, Krisna

Boots, shoes, and leggings

364DIG1, 3642318, 3642624, 3642629, G06F 930

Patent

active

054871565

ABSTRACT:
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

REFERENCES:
patent: 4626989 (1986-12-01), Torii
patent: 4675806 (1987-06-01), Uchida
patent: 4722049 (1988-01-01), Lahti
patent: 4803615 (1989-02-01), Johnson
patent: 4807113 (1989-02-01), Matsumoto et al.
patent: 4807115 (1989-02-01), Torng
patent: 5146570 (1992-09-01), Hester et al.
patent: 5226126 (1993-07-01), McFarland et al.
Sohi; "Instruction Issue Logic for High-Performance, Interruptable, Multiple Function Unit, Pipelined Computers"; IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1990.
IEEE Transactions on Computers, vol. 37, No. 5, May 1988, New York, US, pp. 562-573, Smith & Pleszkun "Implementing Precise Interrupts in Pipelined Computers", pp. 566-568, Sections IV-VI.
IEEE Transaction on Computers, vol. 36, No. 9, Sep. 1986, New York, US, pp. 815-828, Actosta et al. "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors", p. 817, Section IV.
4th Annual Symposium on Computer Architecture 23 Mar. 1977, Long Beach, US., pp. 29-34, Ramseyer & Van Dam "A Multi-Microprocessor Implementation of a General Purpose Pipelined CPU", p. 30, Section 3.
11th Annual International Symposium on Computer Architecture 5 Jun. 1984, Michigan, US, pp. 110-118, Weiss & Smith "Instruction Issue Logic for Pipelined Supercomputers".

Affiliated with

Also associated with

Rating

Processor architecture having independently fetching issuing and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor architecture having independently fetching issuing and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor architecture having independently fetching issuing and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1510838