Processor architecture

Details Processor architecture Processor architecture

2005-05-03

2005-05-03

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

Reexamination Certificate

active

06889317

ABSTRACT:
An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

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Liebchen, A. et al., “Dynamic Reordering of High Latency Transactions Using a Modified Micropipline”, pp. 336-340, XP000344638, Oct. 11, 1992.

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