Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-04-28
2003-07-22
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C174S255000
Reexamination Certificate
active
06596948
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a processor assembly and, more particularly, to an integral processor and power supply assembly.
BACKGROUND OF THE INVENTION
Processing circuits and other electronic circuits generally require direct current (DC) voltages that are stable and free of transients. Accordingly, the processing circuits and other electronic circuits need to be electrically connected to power supplies that are stable and free of transients. Transients and other variations in the DC power supplies can cause the processing and other electronic circuits to experience anomalies or failures.
High speed and large scale processing circuits are very susceptible to problems caused by voltage variations. Some of these voltage variations are caused by load transient currents and other variations in the DC power supplies. Transient currents react with inherent inductance to create voltage variations, wherein the voltage variations are proportional to the inductance and the derivative of the current over time.
Processing circuits rely on very precise, high speed clock signals to control data signals that pass throughout the processing circuit. The clock and data signals are voltages that are in either a logical “high” state, a “low” state. Transient currents (sometimes referred to herein simply as “transients”) on the DC power supplies can cause the clock and data voltages to be falsely interpreted by the receiving circuits as high or low. An erroneously or falsely interpreted clock signal results in the improper flow of data throughout the processing circuit, which may cause the data signals to be improperly processed. An erroneously or falsely interpreted data signal results in an improper data value being processed.
As processing circuits become faster, their clock signal frequencies and the load transient currents increase. In addition, the magnitude of the clock operating voltages decreases. For example, a high frequency clock may use a voltage of 1.3 volts. The increased frequencies of the clock signals result in a decrease in the periods that the clock and data signals are in either the high states or the low states. This limited period at a given state, coupled with a lower operating voltage, increases the criticality of voltage variations on the clock operating voltage. Thus, a very small voltage variation is able to force a clock or data signal into the wrong state. Accordingly, a processing circuit using a high frequency clock is very susceptible to errors caused by relatively small transients and other voltage variations in the DC power supplies. Without very well regulated and stable DC power supplies, the clock speeds and, thus, the processing capabilities of processing circuits are limited.
One method of reducing transients on the power supplied to a processing circuit is by physically locating the power supply close to the processing component, or components, of the processing circuit. This close proximity reduces the distance of the conductors between the power supply and the processing component, which in turn reduces the inductance of the conductors. The length of a conductor is often referred to as the net length. The reduced net lengths reduce inductance and, thus, voltage variations are reduced.
Locating the power supply physically close to the processing component, however, creates additional problems that degrade the performance of the processing circuit. For example, the close proximity of the power supplies to the processors forces other components, such as memory interface circuitry, remote input/output interface circuitry, crossbar communication circuitry, and clock distribution circuitry, to be placed farther away from the processors and, thus, creates performance bottlenecks in each of these varied, yet important computer subsystems. For example, memory components may have to be located a greater distance from the processing component. Accordingly, the net lengths associated with these components increase. The increased net lengths increases the latency between the processing component and its associated components, which slows the processing circuit. For example, a component may require several cycles of the clock in order to respond to a signal received from the processing component.
Other problems occur when the power supply and the processors are located in close proximity to each other. For example, both the power supply and the processing component generate relatively large quantities of heat. When the power supply is physically located near the processing component, a high density of heat is created in the vicinity of the processing component. This heat adversely affects the processing component, i.e., high-temperatures negatively affect silicon transistor switching times and severely degrade the operational frequency of the processor. Adequately removing the heat requires the use of relatively sophisticated and expensive cooling systems, such as refrigerated or cryogenically cooled systems. These cooling systems increase the cost and complexity of the processing circuit as well as decreasing the reliability of the processing circuit.
One method of overcoming the problems of component density and routing resources in processing circuits is to have separate printed circuit board assemblies for the processing and memory subsystems. The separate subsystems, however, compromise the performance of the processing to memory interface. Latency across multiple connectors and multiple boards is high, and bandwidth is reduced. Accordingly, the highest attainable performance is not able to be achieved.
The above-described problems have limited the capabilities of processing and other electronic circuits. Therefore, a need exists for a processing circuit that has a reduced susceptibility to voltage variations and that has processing components located within close proximity to each other.
SUMMARY OF THE INVENTION
The invention is directed toward a processing circuit having minimal susceptibility to voltage variations caused by load transient currents and other sources. The processing circuit may, as an example, comprise a multilayered printed circuit board having processors, memory devices, and other associated electronic components electrically connected thereto. A power supply circuit may be located on a separate printed circuit board that may be electrically connected to the processing circuit.
The multilayered printed circuit board may be formed from a plurality of alternating conductive and insulating layers. Electric power is supplied to components one the printed circuit board by way of a plurality of conductive layers (sometimes referred to as power planes). The processing circuit may have identical power planes located on adjacent conductive layers. The multiple power planes increase the capacitance and decrease the inductance between the power supply and the components, which reduces transients on the power planes. The power planes may also be split so that each layer has power planes associated with different power sources. The split power planes increase the inductance associated with the power supplies because the effective widths of planes are reduced and, thus, voltage variations increase as transients increase on the power planes. This inductance may be offset, however, by the increased capacitance.
Capacitors may be located on the printed circuit board in the vicinity of processing components and may “ring” or encircle the processors and other electronic components. The capacitors may be electrically connected between the power planes and their respective grounds. The capacitors serve to reduce the voltage variations on the power planes caused by the transients from the processing components. Inductance exists between each capacitive element and the power plane, which is determined by the number of connecting vias and their respective geometries. Several vias may pass between each capacitor and the conductive planes, which further reduces the inductance associated with the power supplies. The multiple vias
Day Michael C.
Haden Stuart C.
Harris Shaun L.
Pallotti Lisa Heid
Hewlett--Packard Development Company, L.P.
Norris Jeremy
Talbott David L.
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