Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2011-07-26
2011-07-26
Kindred, Alford W (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S208000
Reexamination Certificate
active
07987343
ABSTRACT:
A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.
REFERENCES:
patent: 5416911 (1995-05-01), Dinkjian et al.
patent: 5867684 (1999-02-01), Kahle et al.
patent: 6138223 (2000-10-01), Check et al.
patent: 6671794 (2003-12-01), Giamei et al.
patent: 2006/0095678 (2006-05-01), Bigelow et al.
“Efficient Handling of Load Multiple Instruction”, IBM Technical Disclosure Bulletin, Sep. 1982, US.
“Use of Load Bypass on Load Multiple Instruction to Reduce Address Generation Interlock Delays”, IBM Technical Disclosure Bulletin, Oct. 1982, US.
z/Architecture. “Principles of Operation”. Sixth Edition (Apr. 2007). IBM. 1218 pages.
Alexander Khary J.
Busaba Fadi Y.
Kapadia Vimal M.
Shum Chung-Lung Kevin
Campbell John
Cantor & Colburn LLP
International Business Machines - Corporation
Kindred Alford W
Moll Jesse R
LandOfFree
Processor and method for synchronous load multiple fetching... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor and method for synchronous load multiple fetching..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor and method for synchronous load multiple fetching... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2697333