Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-08-31
2003-12-30
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S521000
Reexamination Certificate
active
06671708
ABSTRACT:
TECHNICAL FIELD
The present invention relates to arithmetic units which perform multimedia signal processing at higher speed, and to an image processing apparatus using the arithmetic unit.
BACKGROUND ART
Prior art program-controlled processors (arithmetic units) mount vector instructions, thereby obtaining higher performance. A prior art arithmetic unit shown in
FIG. 14
comprises a program control circuit
1401
which decodes a vector instruction and outputs a first start signal and a second start signal, a first address generator
1402
which outputs a first address in accordance with the first start signal, a first data memory
1403
which outputs first data on the basis of the first address, a pipeline operation circuit
1404
which executes a pipeline operation on the basis of the first data, a second address generator
1405
which outputs a second address in accordance with the second start signal, and a second data memory
1406
which contains a result of the operation by the pipeline operation circuit
1404
on the basis of the second address.
As shown in
FIG. 14
, in this arithmetic unit, when the vector instruction is decoded by the program control circuit
1401
, the first start signal is output by the program control circuit
1401
, and the generation of N addresses is started by the first address generator
1402
in accordance with the first start signal. The first data memory
1403
which receives the N addresses supplies N pieces of data to the pipeline operation circuit
1404
. The pipeline operation circuit
1404
receives the supplied N pieces of data and executes the pipeline operation processing.
In addition, the program control circuit
1401
outputs the second start signal in a timing when initially processed data are output from the pipeline operation circuit
1404
, and the second address generator
1405
outputs N addresses to the second data memory
1406
in accordance with the second start signal. Accordingly, operation results which are output by the pipeline operation circuit
1404
are successively stored in the second data memory
1406
.
Then, when the output of the N pieces of data is finished, the first address generator
1402
and the second address generator
1405
output a first end signal and a second end signal to the program control circuit
1401
, respectively, thereby terminating the vector instruction.
In the case of applications requiring a very high operation performance such as real time image processing, general pipeline operation circuits sometimes do not have sufficiently high operation performances. In this case, the operation performance is increased by a hybrid structure in which specific high load operations are performed by dedicated pipeline operation circuits (such as a DCT (Discrete Cosine Transform) operation circuit) and other processings are performed by the general arithmetic circuits, thereby ensuring the real time processing. However, the required dedicated pipeline operation circuits vary with the contents to be processed. Therefore, the program control circuit has timing designs which are inherent in respective dedicated pipeline operation circuits. In other words, the timing designs are specific to respective applications. Considering the age of IP (Intellectual Property) which will come in the future, it is a large problem that the program control circuit which is the most complex part in the processor should be changed according to purposes.
The present invention is made in view of this problem, and it provides an arithmetic unit having a structure which is divided into a general arithmetic circuit and a dedicated arithmetic circuit to prevent the change in the dedicated arithmetic circuit for each purpose from affecting the general arithmetic circuit, whereby the unit can be applied to various applications, and image processing apparatus using the arithmetic unit.
DISCLOSURE OF THE INVENTION
An arithmetic unit according to one embodiment the present invention has a general arithmetic circuit and a dedicated arithmetic circuit, the general arithmetic circuit mounts plural vector instructions and executes a pipeline operation on tile basis of the vector instructions together with the dedicated arithmetic circuit. In the arithmetic unit, the general arithmetic circuit outputs: a dedicated pipeline operation circuit selection signal notifying a contest of arithmetic in the dedicated arithmetic circuit; plural operation results of the general arithmetic circuit; and a general arithmetic circuit output data enable signal notifying an output timing of the plural operation results, to the dedicated arithmetic circuit. The general arithmetic circuit receives: plural dedicated operation results of the dedicated arithmetic circuit; and a dedicated arithmetic circuit output data enable signal for recognizing an output timing of the plural dedicated operation results and a termination timing of the output data, from the dedicated arithmetic circuit. The dedicated arithmetic circuit comprises: plural dedicated pipeline operation circuits each outputting a signal notifying a number of pipeline stages and executing a pipeline operation for the plural operation results of the general arithmetic circuit; a data selection circuit for arbitrarily selecting dedicated operation results which are output by one of the plural dedicated pipeline operation circuits, from dedicated operation results which are respectively output by the plural dedicated pipeline operation circuits, in accordance with the dedicated pipeline operation circuit selection signal of the general arithmetic circuit, and outputting the arbitrarily selected dedicated operation results as the plural dedicated operation results to the general arithmetic circuit; and a control circuit for receiving the signals each notifying the number of pipeline stages, each of which signals is output by each of the plural dedicated pipeline operation circuits, and the dedicated pipeline operation circuit selection signal and the general arithmetic circuit output data enable signal of the general arithmetic circuit, and outputting the dedicated arithmetic circuit output data enable signal to the general arithmetic circuit.
According to the above-described structure, the arithmetic unit can mount an arbitrary dedicated pipeline operation circuit which is suitable for each purpose without changing the program control circuit, regardless of the structure of the general arithmetic circuit. Consequently, the arithmetic unit which can be applied to the various applications can be realized.
An arithmetic unit according to another embodiment of the present invention has a general arithmetic circuit and a dedicated arithmetic circuit, the general arithmetic circuit mounts plural vector instructions and executes a pipeline operation on the basis of the vector instructions together with the dedicated arithmetic circuit. The general arithmetic circuit comprises: a program control circuit for outputting a first start signal, a second start signal, a first operation circuit selection signal, a second operation circuit selection signal, a dedicated pipeline operation circuit selection signal and a general arithmetic circuit output data enable signal, and receiving a dedicated arithmetic circuit output data enable signal; a first address generator for continuously outputting M first addresses on the basis of the first start signal from the program control circuit; a first data memory for outputting M pieces of first data on the basis of the first addresses from the first address generator; a first pipeline operation circuit for executing a pipeline operation for the first data from the first data memory and successively outputting M first operation results, in accordance with the first operation circuit selection signal from the program control circuit; a second pipeline operation circuit for executing a pipeline operation for second operation results from the dedicated arithmetic circuit and successively outputting M third operation results, in accordance with the second operation circuit sele
Hamada Mana
Kuromaru Shunichi
Matsuo Masatoshi
Nakamura Tsuyoshi
Oohashi Masahiro
Do Chat C
Matsushita Electric - Industrial Co., Ltd.
Ngo Chuong Dinh
Wenderoth , Lind & Ponack, L.L.P.
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