1996-07-22
1999-02-09
Coleman, Eric
39580023, 39580024, G06F 926
Patent
active
058706186
ABSTRACT:
An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.
REFERENCES:
patent: 5101489 (1992-03-01), Sato et al.
patent: 5437043 (1995-07-01), Fujii et al.
patent: 5513363 (1996-04-01), Kumar et al.
Microprocessor Report, "Philips Hopes to Displace DSPs with VLIW", Brian Case, Dec. 5, 1994, pp. 12-15.
Microprocessor Report, "UltraSpace Adds Multimedia Instructions", Linley Gwennap, Dec. 5, 1994, pp. 16-18.
Fujikawa Yoshifumi
Ishiguro Masao
Kojima Keiji
Nishioka Kiyokazu
Nojiri Tohru
Coleman Eric
Hitachi , Ltd.
Monestime Mackly
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