1985-06-04
1988-04-12
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 900
Patent
active
047379324
ABSTRACT:
A processor includes a central processing unit (CPU), a local memory and a local memory access device which are coupled to an internal bus, and an input/output (I/O) interface adapted to couple the internal bus to a system bus. The CPU generates a request signal for access to an external device coupled to the system bus and receives an acknowledgment signal for designating grant of usage of the system bus. The CPU releases the internal bus during the period of time from generation of the request signal until reception of the acknowledgment signal. Thus, the local memory access device can access the local memory during the period.
REFERENCES:
patent: 4375639 (1983-03-01), Johnson, Jr.
patent: 4414624 (1983-11-01), Summer et al.
patent: 4481572 (1984-11-01), Ochsner
patent: 4494193 (1985-01-01), Brahm et al.
Mills John G.
NEC Corporation
Shaw Gareth D.
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