Processing unit using truth-valued flow

Details Processing unit using truth-valued flow Processing unit using truth-valued flow

1989-12-04

1992-08-25

Fleming, Michael R.

395900, G06F 1518

Patent

active

051426641

ABSTRACT:
A truth-valued-flow processing unit according to the invention comprises truth value generator circuits truth-valued-flow inference units a truth value converter, a first bus and a second bus. The first bus is provided in a number equal to the number of kinds of input variables. The second bus comprises a number of lines equal to the number of kinds of a plurality of predetermined functions used by the consequents of implications. The truth value generator circuit is provided in a number equal to the number of kinds of input variables. Each truth value generator circuit is connected at an output side thereof to a corresponding one of the first buses, generates truth values and outputs the truth values on the corresponding first bus. Each truth-valued-flow inference unit is connected at an input side thereof to all of the first buses and at an output side thereof to one line of the second bus, selects, from all truth values outputted by the plurality of truth value generator circuits prescribed ones of the truth values in accordance with predetermined rules and subjects these truth values to a prescribed operation. The truth value converter causes the truth values outputted by the plurality of truth-valued-flow inference units to act upon each of the plurality of functions used by the consequent, thereby providing an output representing inferential results.

REFERENCES:
patent: 4837725 (1989-06-01), Yamakawa
patent: 4875184 (1984-10-01), Yamakawa
Yamakawa et al., "Fuzey Memory Device", Preprints of Second IFSA Congress Tokyo, Jul. 20-25 1987, pp. 551-555.
Yamakawa, "A Simple Fuzey Computer Hardware System Employing Min & Max Operations", Preprints of Second IFSA Congress Tokyo, Jul. 20-25, 1987, pp. 827-830.

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