Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1996-10-11
2001-10-30
Banankhah, Majid (Department: 2151)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C345S502000, C345S558000
Reexamination Certificate
active
06311204
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to video, audio, graphics, input/output and other processing functions in set top box applications. More particularly, the present invention relates to a processing system with an application specific integrated circuit (ASIC) processor which provides video, audio, graphics and input/output processing functions and is particularly well-suited for use in set top box applications.
BACKGROUND OF THE INVENTION
Multimedia distribution systems are becoming increasingly important vehicles for delivering video, audio and other data to and from remote users. Such distribution systems include cable or community access television (CATV) systems, telephone systems and computer networks. A set top box may be used as an interface between the distribution system and a television set, computer or other type of remote user terminal. The set top box typically provides functions such as input/output processing of video, audio and other data, audio and video demultiplexing and decompression, graphics overlay processing for use in electronic program guides and the like, entitlement control for video on demand (VOD), near video on demand (NVOD) and pay-per-view (PPV) applications, and remote control user interfaces.
A conventional set top box generally provides the above-noted functions using a multiplicity of dedicated stand-alone integrated circuits, each having its own separate support circuitry and protocols to provide, for example, memory access and other processing functions. This may be attributed in part to the fact that many of the circuits used in set top box applications are general-purpose devices designed to support a broad array of applications. As a result, there is considerable overlap in many of the circuit functions, as well as potential incompatibilities which lead to slower processing speed and other inefficiencies. The conventional set top boxes are therefore not only unduly complex and expensive, but also fail to provide optimal levels of performance. Widespread implementation of multimedia distribution systems using cable, telephone and/or computer networks will depend in large part upon reducing the complexity and cost of set top box hardware.
As is apparent from the above, there is a need for an improved processing system suitable for use in set top box applications and which can be configured to utilize shared processing hardware to thereby provide video, audio, graphics, input/output communication and other functions with improved efficiency and reduced cost and complexity.
SUMMARY OF THE INVENTION
The present invention involves apparatus and methods for providing video, audio, graphics, input/output communication and other processing functions in set top boxes and other applications with reduced cost and complexity. In one embodiment, the invention is implemented as an application-specific integrated circuit (ASIC) processor suitable for use in a set top box or other processing system to improve hardware efficiency and throughput performance relative to conventional systems.
One aspect of the invention involves a method and apparatus for prescaling graphics data for use in a graphics overlay operating mode. In an exemplary embodiment, a method and apparatus are provided for processing a stream of RGB pixel data in a graphics processor. The RGB pixel data for a given pixel are first converted to luminance and chrominance data for that pixel. The luminance and chrominance data are then prescaled by a blending value associated with the given pixel. An interpolation operation is performed on the luminance and chrominance data as well as on the blending value for the given pixel using corresponding luminance and chrominance data and blending values for at least one other pixel in the stream. This interpolation may include operations such as horizontal filtering and may also include chroma filtering to convert the luminance and chrominance data into a 4:2:2 chrominance format compatible with MPEG-2 video. The interpolation operation produces interpolated luminance and chrominance data and an interpolated blending value for the given pixel. A video signal to be combined with the graphics data is then scaled using the interpolated blending value. The scaled video signal is combined with the interpolated luminance and chrominance data for the given pixel to provide a combined video/graphics signal suitable for display.
Another aspect of the invention involves a technique for dynamic alteration of a color look-up table (CLUT) pallet identifier in response to one or more key codes placed in an input data stream. In an exemplary embodiment, a method and apparatus are provided for converting an input data stream including a sequence of input data blocks into a converted stream suitable for addressing a look-up table. The look-up table may be a 256×16 table which requires an 8-bit address to identify a particular table entry. The present invention allows such a table to be addressed using 4-bit data blocks in the input data stream. For each received 4-bit data block in the input data stream, a determination is made as to whether that block corresponds to a predetermined key value. If a given input block does not correspond to the predetermined key value, the 4-bit input block is combined with a previously-stored 4-bit pallet identifier to generate an 8-bit address into the look-up table. The pallet identifier specifies one of 16 different 16-entry pallets within the 256×16 look-up table. If the given input block does correspond to the key value, a new 4-bit pallet identifier is stored. The new pallet identifier may be contained within a data block which immediately follows the key value block in the data stream. The new pallet identifier is then used in combination with subsequent 4-bit data blocks in the stream to generate 8-bit addresses into the look-up table. This arrangement provides substantial improvements in table addressing efficiency and is particularly well-suited for use in graphics processors which generate graphics data using color look-up tables.
Another aspect of the invention relates to a technique for permitting simultaneous utilization of two system clocks in applications in which certain processing system elements utilize one system clock operating at a non-integer multiple of another system clock used by other processing system elements. For example, a processing system may include a video decoder and/or an NTSC encoder which operate with a first clock at 27 MHz. The processing system may also include an ASIC processor operating with a second clock at 40.5 MHz. A synchronous phase detector is used to generate a clock enable signal suitable for use in a pipeline structure to facilitate data transfer between the different elements of the processing system. An exemplary circuit may include two or more D-type flip-flops or other data storage devices. The first clock signal is applied to a clock input of a first data storage device, and the second clock is applied to a data input of the first data storage device. The second clock is also applied to a clock input of at least one additional data storage devices connected in series with the first data storage device. The output of the first data storage device is applied to the data input of a second data storage device, the output of the second is applied to the data input of a third, and so on. The clock enable signal is provided at the output of the fourth data storage device. The clock enable signal includes phase information extracted from the first and second clock signals, and is suitable for use in driving one or more multiplexers in a pipeline structure or other state-based logic device to thereby allow data transfer between an element of the processing system operating at the first clock rate and an element operating at the second clock rate.
Another aspect of the invention involves a differential video data encoding technique which utilizes a reduced number of bits per pixel to encode chroma and luma components of a video data stream. I
Banankhah Majid
C-Cube Semiconductor II Inc.
Proskauer Rose LLP
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