Processing system with memory arbitrating between memory access

Details Processing system with memory arbitrating between memory access Processing system with memory arbitrating between memory access

1996-10-11

1999-03-30

Ramirez, Ellis D.

39580042, G06F 1700

Patent

active

058899499

ABSTRACT:
A method and apparatus for providing memory arbitration which allows multiple hardware functions implemented in a single ASIC to utilize a single shared memory unit or multiple shared memory units. The memory arbitration technique establishes a priority among multiple memory access requesters and is particularly well-suited for use in a set top box processing system. A plurality of memory access requests are received from a plurality of processing elements in a set top box processing system. The processing elements include a transport stream demultiplexer, a host central processing unit and a graphics processor. The processing elements are permitted to access a shared memory in accordance with an established priority. The established priority assigns a higher priority to the graphics processor than to the host central processing unit, and may be in the order of graphics processor, transport stream demultiplexer, and central processing unit.

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"New Single-chip DSP Solution for the digital set-top box standards"; Texas Instruments, 1997.
"Architecture of MPEG-2 Digital Set-Top-Box for CATV VOD System"; by Kiyoshi Kohiyama et al; IEEE 1996 pp. 324-325.
I.B.M. Microelectronics; "The Challeges of contingence for Set-Top-Box Manufacturers" pp. 1-9.

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