Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2003-06-24
2008-08-19
Dollinger, Tonia L. M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S225000
Reexamination Certificate
active
07415594
ABSTRACT:
A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.
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Chase Craig M.
Doerr Michael B.
Gibson David A.
Hallidy William H.
Coherent Logix, Incorporated
Dollinger Tonia L. M.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Petro Anthony M.
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