Processing system with dynamically allocatable buffer memory

Details Processing system with dynamically allocatable buffer memory Processing system with dynamically allocatable buffer memory

1997-12-05

2000-06-27

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

712 23, 712 29, 712 36, 711111, 711121, G06F 1300

Patent

active

060818832

ABSTRACT:
A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks. Upon receiving requests for data from the NP, the FSP checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request. The resulting scalable computer provides higher data availability, faster access to shared data, and reduced administrative costs via data consolidation.

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