Processing system with dual buses

Details Processing system with dual buses Processing system with dual buses

1979-04-02

1981-01-13

Smith, Jerry

Excavating

371 8, 371 49, G06F 1114, G06F 1110

Patent

active

042453445

ABSTRACT:
A processing system is disclosed in which transfers between processors and memory are made on dual redundant buses. In a transfer, the transmitting unit sends the same information simultaneously on each of the buses. The receiving unit makes parity checks on each bus, and compares the information received on one bus with that received on the other bus. The receiving unit includes means for implementing a decision rule, based on these checks and comparison, to choose from which bus to take information, if either.

REFERENCES:
patent: 3476922 (1969-11-01), Yiotis
patent: 3781795 (1973-12-01), Zegers
patent: 3978327 (1976-08-01), Huber
patent: 3999053 (1976-12-01), Dalmasso
patent: 4017828 (1977-04-01), Watanabe et al.

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