Processing system having testing mechanism

Details Processing system having testing mechanism Processing system having testing mechanism

1997-06-18

1999-04-27

Tu, Trinh L.

Excavating

371 2234, G01R 3128

Patent

active

058987045

ABSTRACT:
A processing system having a testing mechanism that can read out data from a memory such as a ROM without increasing the number of logic circuits to simplify the circuit construction by utilizing the testing mechanism. The processing system includes an address register in the testing mechanism of a chip part connected to the memory in parallel with the other registers, a selector for selecting and sending out either test data from the testing mechanisms or read-out data from the memory. A control unit is further provided so as to set a leading address of the data to be read out from the memory to the address register by the shift operation, to switch the selector to send out the read-out data from the memory, and then, to count up the address of the address register in accordance with a data number to read out, and to read out the data from the memory. This processing system can be applied to a system having the testing mechanism of a JTAG circuit and the like.

REFERENCES:
patent: 5377198 (1994-12-01), Simpson et al.
patent: 5477493 (1995-12-01), Danbayashi
patent: 5673276 (1997-09-01), Jarwala et al.
patent: 5706297 (1998-01-01), Jeppensen, III et al.
patent: 5768289 (1998-06-01), James

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